Feed-Forward Delta-Sigma ADC with Fewer Amplifiers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Delta-sigma modulator-based ADCs require multiple amplifiers and feed-forward paths, leading to increased power consumption and die area usage due to the complexity of the loop filter and summer components.
Innovation Solution
Incorporating a switched-capacitor integrator stage with a capacitive feedback network that reduces the number of amplifiers and feed-forward paths by using a second-order operation with two series-connected capacitors and a shunt capacitor network, which integrates charge and provides a reduced dynamic range requirement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional feed-forward delta-sigma modulator is used with multiple integrator stages and a summer, then the ADC achieves accurate signal conversion, but the number of amplifiers and circuit complexity increase
Solution Approach 1:
The patent combines multiple integrator stages into a single switched-capacitor integrator stage that performs second-order integration. The capacitive feedback network with series-connected capacitors C1 and C2 replaces what would traditionally require multiple separate integrator amplifiers, merging their functions into one amplifier while achieving the same fourth-order loop filter effect.
Solution Approach 2:
The single switched-capacitor integrator stage with capacitive feedback network performs multiple functions: it provides second-order integration, implements the feedback path, and replaces the need for separate summer components. This multi-functional design reduces the overall number of amplifiers required in the system.
2Measurement precision
If multiple amplifiers and feed-forward paths are used in the loop filter, then the ADC achieves high-order filtering, but power consumption increases
Solution Approach 1:
The patent merges multiple amplifier functions into a single switched-capacitor integrator amplifier. By using the capacitive feedback network with series capacitors C1 and C2, the system achieves fourth-order filtering effects that would traditionally require multiple amplifiers, thereby reducing power consumption while maintaining high-order filtering capability.
Solution Approach 2:
The patent changes the operational parameters by using switched-capacitor techniques instead of traditional continuous-time amplifiers. The capacitive feedback network with intermittent coupling to reference voltage sources allows the system to achieve high-order filtering with lower power consumption by utilizing capacitor charging/discharging cycles rather than continuous amplifier operation.
3Measurement precision
If a summer with high dynamic range is used to combine integrator outputs, then the ADC achieves accurate quantization, but die area usage increases
Solution Approach 1:
The patent eliminates the need for a separate summer component by integrating the summing function into the switched-capacitor integrator stage. The capacitive feedback network naturally sums the feedback signal with the input signal through capacitor charge accumulation, removing the need for additional summing amplifiers and reducing die area usage.
Solution Approach 2:
The patent extracts the summer function from the traditional architecture and integrates it into the integrator stage itself. By taking out the separate summer component and incorporating its functionality into the switched-capacitor integrator with capacitive feedback, the design reduces the number of discrete components and decreases overall die area while maintaining quantization accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces circuit complexity and power consumption while maintaining accurate signal representation, achieving a fourth-order loop filter with only two integrator stages and two amplifiers, thus lowering overall power usage and die area requirements.
Implementation Method 1
The capacitive feedback network includes at least two capacitors coupled in series at a common terminal that is intermittently coupled to a reference voltage source by a switched-capacitor shunt network
Data Source
AI summary
An analog-to-digital converter (ADC) having a reduced number of amplifiers and feed-forward signal paths provides for reduced complexity and power consumption. The analog-to-digital converter includes a delta-sigma modulator having a loop filter with second-order stages implemented with a single amplifier each, provided by a series-connected capacitive feedback network with a switched capacitor shunt. The reduction in the amplifier stages reduces the number of inputs to, and dynamic range required from, the summing node that provides input to the quantizer, as well as reducing the power requirements and complexity of the circuit due to the reduced number of amplifiers.