Feed-Forward Clock Recovery for Jitter and Frequency Shifts
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Solution Overview
Problem
Existing clock data recovery methods for high data rates, particularly for n-ary signals like PAM-n, face challenges with latency issues due to feedback structures and are inadequate in handling jitter and large frequency variations, especially in spread spectrum clocking modulations.
Innovation Solution
A feed-forward structure is employed for clock data recovery, utilizing edge timings and modulo transformations to estimate a reference clock signal, with modules like accumulation and compensation calculation, offset selection, and front clock generation, enabling recovery of clock signals even at data rates higher than 10Gbps with system clock rates of 250 MHz.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase-locked loop (PLL) based clock data recovery is used, then clock signal recovery is achieved, but latency issues occur due to feedback structure
Solution Approach 1:
The patent inverts the traditional feedback-based PLL approach by using a feed-forward structure. Instead of using feedback to correct phase errors, the invention uses feed-forward phase interpolation to predict and generate the correct clock phase based on detected edge positions, thereby eliminating latency while maintaining reliable clock recovery
Solution Approach 2:
The patent performs preliminary action by detecting edge positions and calculating required phase shifts before the clock signal is actually needed. The phase interpolation is computed in advance based on accumulated edge timing information, allowing the system to generate accurate clock phases without waiting for feedback loops
2Adaptability or versatility
If phase interpolation techniques are used to track frequency shifts, then frequency tracking capability is improved, but the system becomes critical with regard to latency due to feedback
Solution Approach 1:
The patent converts the feedback-based phase interpolation into a feed-forward mechanism. The system detects edge positions, calculates the phase deviation, and directly applies the required phase shift to generate the interpolated clock signal, eliminating feedback latency while maintaining frequency tracking capability
Solution Approach 2:
The patent uses a simple counter-based edge detection mechanism that processes each edge event independently and discards it after processing. This disposable approach to edge handling allows rapid frequency adaptation without the overhead of maintaining complex feedback state, reducing latency while preserving frequency tracking
3Loss of time
If blind oversampling with high sampling rate is used, then feedback is eliminated, but larger frequency shifts due to spread-spectrum clocking modulations cannot be handled
Solution Approach 1:
The patent implements a simplified feedback mechanism that only monitors edge positions and accumulates timing deviations. This minimal feedback approach provides just enough information to calculate frequency shifts and adjust phase interpolation, eliminating the need for high-rate blind oversampling while maintaining adaptability to frequency variations
Solution Approach 2:
The patent dynamically changes the sampling phase based on detected edge positions and calculated frequency deviations. By adapting the sampling parameters (phase and timing) according to the actual signal characteristics, the system can handle large frequency shifts without requiring excessively high fixed sampling rates
4Loss of time
If analog components are used in PLL based clock recovery, then major delays in feedback are avoided, but device complexity increases
Solution Approach 1:
The patent replaces the mechanical/analog PLL feedback system with a digital feed-forward phase interpolation mechanism. Instead of using analog phase detectors, charge pump circuits, and voltage-controlled oscillators, the invention uses digital edge detection, counter-based timing measurement, and lookup table phase interpolation, achieving similar delay reduction with simpler digital logic
Data Source
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AI summary
A method for recovering a clock signal from a data signal by using a clock recovery module (10) is described. Edge timings of the data signal are accumulated. The edge timings accumulated are transformed into one reference bit period. A time offset for the reference bit period is determined. A reference clock signal is determined based on the time offset. The number of bits within a system clock of the clock recovery module (10) is determined. The clock signal is recovered based on the reference clock signal and the number of bits. Further, a clock recovery module (10) as well as a computer program (32) are described.