Feed Forward Equalizer Summing Circuit Power Efficiency
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Solution Overview
Problem
Feed forward equalizers face challenges in achieving efficient equalization due to high power consumption and parasitic capacitance, leading to difficulties in smooth operation and accurate data signal transmission, especially in high-speed data transmission systems where inter-symbol interference (ISI) is prevalent.
Innovation Solution
The proposed feed forward equalizer design includes a series of delay circuits, filters, and a summing calculator that performs equalization using only a summing operation without subtraction, reducing area occupation and power consumption by utilizing a driver with a pull-up and pull-down circuit, and minimizing noise effects from power supply and transistor mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If resistance is added for linearity and impedance matching, then equalization performance is improved, but power consumption increases and parasitic capacitance is introduced
Solution Approach 1:
The patent extracts and eliminates the subtraction operation from the equalization process, keeping only the summing operation. This removes the need for additional resistance components that cause power consumption and parasitic capacitance, while maintaining equalization performance through the simplified summing-based calculation structure.
Solution Approach 2:
The patent changes the operational parameters by using only summing operations instead of both summing and subtraction operations. This parameter change allows the removal of resistance elements that contribute to power consumption and parasitic capacitance, achieving low-power equalization without sacrificing performance.
2Reliability
If resistance is added for linearity and impedance matching, then equalization performance is improved, but unintentional power leakage occurs
Solution Approach 1:
The patent extracts and eliminates the subtraction operation from the equalization process, keeping only the summing operation. This removes the need for additional resistance components that cause power consumption and parasitic capacitance, while maintaining equalization performance through the simplified summing-based calculation structure.
3Reliability
If complex equalization operations are performed, then data signal quality is improved, but device area increases
Solution Approach 1:
The patent extracts and eliminates the subtraction operation from the equalization process, keeping only the summing operation. This removes the need for additional resistance components that cause power consumption and parasitic capacitance, while maintaining equalization performance through the simplified summing-based calculation structure.
Solution Approach 2:
The patent merges the reference output directly into the summing calculation without requiring separate subtraction paths. This consolidation reduces the number of discrete components and interconnections needed, thereby reducing device area while maintaining equalization functionality.
4Measurement precision
If noise from power supply and transistor mismatches is present, then calculation accuracy is degraded, but eliminating subtraction operations reduces this noise
Solution Approach 1:
The patent extracts and eliminates the subtraction operation from the equalization process, keeping only the summing operation. This removes the need for additional resistance components that cause power consumption and parasitic capacitance, while maintaining equalization performance through the simplified summing-based calculation structure.
Data Source
AI summary
A feed forward equalizer includes a plurality of delay circuits connected to each other in series and configured to delay input signals. A plurality of filters respectively correspond to outputs of the plurality of delay circuits, except for a reference output which is an output of a first delay circuit among the plurality of delay circuits, and the input signals. A calculator configured to sum the reference output and outputs of the plurality of filters. Each of the plurality of filters is configured to receive an output of a delay circuit corresponding thereto, among the plurality of filters, and the reference output.