Feed-Through Via Layout for Low-Capacitance GAA Cells
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Solution Overview
Problem
As semiconductor devices reduce in minimum feature size, high resistance and high capacitance issues arise in traditional routing, particularly due to the coupling capacitance caused by floating metal gates in gate all around (GAA) field-effect transistors, which degrade device performance.
Innovation Solution
The formation of a wide and short feed-through via is implemented, along with a method to minimize or eliminate coupling capacitance by removing floating metal gates using a continuous poly silicon on diffusion edge (CPODE) process, ensuring efficient signal routing between metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional routing is used in gate all around (GAA) field-effect transistors, then device integration is achieved, but coupling capacitance increases causing high resistance and high capacitance issues that degrade device performance
Solution Approach 1:
The patent removes floating metal gates from the device structure to eliminate the source of coupling capacitance. By extracting these problematic conductive elements, the harmful capacitive coupling between adjacent transistor gates is eliminated, directly resolving the performance degradation issue while maintaining device functionality
Solution Approach 2:
The patent introduces a via structure that extends vertically through the device layers to establish electrical connections in the vertical dimension. This via-based routing approach bypasses the traditional planar metal gate routing, creating a new dimensional pathway for signal transmission that avoids capacitive coupling issues
2Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but additional problems such as high resistance and high capacitance arise
Solution Approach 1:
The patent segments the electrical connection path into multiple discrete components: a via structure for vertical connection and separate metal layers for horizontal routing. This segmentation allows each component to be optimized independently, enabling continued scaling of feature sizes while maintaining reliable electrical connections and avoiding the high resistance and capacitance problems that arise in traditional continuous routing
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a substrate, a plurality of fin structures disposed on the substrate, and a stack of metal gates formed over the plurality of fin structures. The device also includes a cell region defined by a first pair of insulation regions and a second pair of insulation regions, wherein the first pair of insulation regions extend across the stack of metal gates along a first direction, and the second pair of insulation regions extend into the stack of metal gates along a second direction that is perpendicular to the first direction. The device also includes a feed-through via (FTV) extending through the cell region. The FTV includes a frontside via extending from a first side of the substrate through an isolated cell region, and a backside via extending from a second side of the substrate to connect with the frontside via.