Feed-Through Via Layout for Backside IC Routing Flexibility
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Solution Overview
Problem
Existing integrated circuit (IC) designs face challenges in minimizing the use of frontside metal resources while maintaining efficient signal and power supply connections, leading to reduced routing flexibility and increased area requirements.
Innovation Solution
The integration of feed-through vias (FTVs) that directly contact gate electrodes or metal-like segments and extend to the backside of the semiconductor substrate, reducing the need for frontside metal lines and enabling more flexible routing by utilizing backside metal connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frontside metal lines are used for signal and power supply connections, then connection efficiency is maintained, but IC area increases and routing flexibility decreases
Solution Approach 1:
The patent utilizes the third dimension (vertical depth) by implementing backside vias that extend through the substrate from the frontside to the backside of the IC. This allows connections to be established in the vertical dimension rather than relying solely on horizontal metal routing on the frontside, thereby reducing the area required for metal interconnects while maintaining connection efficiency.
Solution Approach 2:
The patent segments the interconnection path into multiple parts: frontside contact regions, backside vias extending through the substrate, and backside metal interconnects. This segmentation allows the connection function to be distributed across different layers and dimensions, reducing the burden on frontside metal resources and enabling more compact layouts.
2Reliability
If frontside metal lines are used for signal and power supply connections, then connection efficiency is maintained, but routing flexibility decreases
Solution Approach 1:
By introducing backside vias that penetrate the substrate vertically, the patent adds a new dimension for routing connections. This enables signals and power to be routed through the substrate depth, providing alternative pathways that are independent of frontside metal line routing constraints, thereby significantly improving routing flexibility while maintaining connection efficiency.
Solution Approach 2:
The interconnection path is segmented into frontside contact regions, backside vias, and backside metal interconnects. This segmentation allows different portions of the connection to be optimized independently: frontside contacts can be placed where needed, vias provide vertical transport, and backside metals handle routing, collectively enhancing overall routing flexibility.
3Area of stationary object
If frontside metal resources are minimized, then IC area decreases and routing flexibility increases, but connection efficiency may be compromised
Solution Approach 1:
The patent compensates for reduced frontside metal resources by transitioning the connection function to the vertical dimension through backside vias. These vias extend through the substrate to establish connections with backside metal interconnects, ensuring that connection efficiency is maintained even with minimal frontside metal usage, while enabling smaller IC area and improved routing flexibility.
Solution Approach 2:
The backside via acts as an intermediary structure that bridges the frontside contact regions and the backside metal interconnects. This intermediary enables efficient signal and power transmission through the substrate without requiring extensive frontside metal routing, thereby maintaining connection efficiency while achieving compact area and enhanced flexibility.
Data Source
AI summary
An IC device includes an active area extending in a first direction in a front side of a semiconductor substrate, a first gate electrode overlying the active area and extending in a second direction perpendicular to the first direction, a metal-like defined (MD) segment extending in the second direction adjacent to the first gate electrode and overlying the active area, and a first feed-through via (FTV) directly contacting one of the first gate electrode or the MD segment and extending in a third direction perpendicular to the first and second directions to a back side of the semiconductor substrate.