Feed-Through Via Layout Selection for OPC-Induced RC Delay
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Solution Overview
Problem
Existing integrated circuit (IC) designs face challenges in minimizing signal delays due to resistance-capacitance (RC) issues, which are exacerbated by optical proximity correction (OPC) processes that alter intended electrical characteristics.
Innovation Solution
Employing a machine learning (ML) model to guide placement and routing (PnR) operations, incorporating OPC-oriented patterns that minimize electrical characteristic deviations, and using marker-guided OPC to optimize patterns for improved manufacturability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If optical proximity correction (OPC) is applied to improve manufacturing precision, then pattern accuracy is improved, but electrical characteristics deviate from intended design
Solution Approach 1:
The patent applies preliminary action by performing electrical characteristic verification and adjustment during the OPC pattern generation phase, before actual fabrication. The system predicts and corrects electrical characteristic deviations caused by OPC, ensuring that the corrected patterns maintain both manufacturing precision and electrical performance.
Solution Approach 2:
The patent implements feedback by using extracted electrical characteristic data from OPC-corrected patterns to iteratively refine the OPC process. The system analyzes deviations between intended and actual electrical characteristics, then adjusts subsequent OPC corrections to minimize these deviations while maintaining pattern accuracy.
2Loss of time
If wiring connections are shortened to reduce signal delays, then signal delay is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies parameter changes by systematically varying wiring routing parameters and geometric configurations to achieve optimal signal delay reduction. The system evaluates multiple routing options with different lengths and configurations, selecting those that minimize RC delays while maintaining manufacturability through standardized design rules and processes.
Data Source
AI summary
A method of manufacturing an integrated circuit (IC) device includes: designing a circuit layout, including a selecting among a first pattern and a second pattern as possible patterns for forming a conductive structure by selecting the pattern that will undergo the least change during optical proximity correction (OPC) of the circuit layout, wherein the selecting the pattern that will undergo the least change during OPC of the circuit layout includes using a machine learning model to predict changes to the first pattern and the second pattern during OPC; and fabricating a lithographic mask that includes a third pattern, the third pattern being obtained by performing OPC on the selected pattern.