Feedback Clock Loss Detection with Dual-Edge Sampling
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Solution Overview
Problem
In digital logic circuits, particularly in FPGAs, the loss of a feedback clock signal to a digital clock manager can lead to logic errors due to the assumption that clock deskew functions are being performed, despite the feedback clock being lost, resulting in undetected issues with the clock distribution network.
Innovation Solution
A method involving a clock divider to produce a divided feedback clock signal, with pairs of flip-flops sampling on both rising and falling edges of the reference clock to detect whether the feedback clock is toggling, using detection logic to assert a status signal only when both pairs indicate the same logic value, thus accurately detecting clock loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single pair of flip-flops samples the feedback clock on one edge of the reference clock, then the detection logic is simpler, but false indications of clock loss may occur due to setup time violations
Solution Approach 1:
The detection circuit is segmented into two independent pairs of flip-flops: a first pair sampling on the rising edge of the reference clock and a second pair sampling on the falling edge. This segmentation allows each pair to operate independently, reducing the complexity of individual detection paths while improving overall reliability through redundant sampling opportunities.
Solution Approach 2:
The detection mechanism uses periodic sampling at both rising and falling edges of the reference clock cycle. By implementing detection at multiple periodic intervals within each clock cycle, the system increases the probability of successfully capturing the feedback clock state without requiring more complex continuous monitoring logic.
2Productivity
If the feedback clock frequency is an integer multiple of the reference clock frequency, then the clock multiplication function is achieved, but the feedback clock may not toggle between consecutive reference clock edges
Solution Approach 1:
The detection system employs periodic sampling at both rising and falling edges of the reference clock. This periodic dual-edge sampling ensures that even when the feedback clock frequency is an integer multiple of the reference clock frequency, the detection mechanism can still capture transitions at appropriate intervals, maintaining accurate clock loss detection capability.
Solution Approach 2:
The detection logic dynamically adapts to different feedback clock frequencies by sampling at both edges of the reference clock cycle. This dynamic approach allows the system to reliably detect clock loss regardless of the multiplication factor, as the dual-edge sampling strategy ensures coverage of all possible transition patterns.
Data Source
AI summary
Method and apparatus for detecting clock loss in clock circuit. An example of the invention relates to detecting loss of a feedback clock signal input to a digital clock manager, where the feedback clock signal is derived from the reference clock signal. A clock divider is provided to produce a divided feedback clock signal from the feedback clock signal. A first pair of flip-flops is configured to store samples of the divided feedback clock signal on consecutive edges of the reference clock signal. A second pair of flip-flops is configured to store samples of the divided feedback clock signal on consecutive edges of an inversion of the reference clock signal. Detection logic is configured to detect whether each of the first pair of flip-flops and each of the second pair of flip-flops store the same value.