Sigma-Delta ADC Feedback DAC With Shaped Current Pulses
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Solution Overview
Problem
Sigma-delta analog-to-digital converters (ADCs) face challenges with clock jitter sensitivity and high DC power consumption due to the characteristics of digital-to-analog converters (DACs) used in their conversion feedback paths, which compromise the design and performance of these converters.
Innovation Solution
A DAC with a capacitor circuit pre-charged to a reference voltage and a resistive circuit that varies resistance during each feedback cycle to control current pulse shape, ensuring consistent charge transfer and reduced peak currents, thereby minimizing clock jitter sensitivity and DC current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a switched current source DAC is used to generate conversion feedback signal, then the DAC can transfer consistent charge in each feedback cycle, but the full-magnitude current at the end of feedback cycle causes high sensitivity to clock jitter
Solution Approach 1:
The patent applies dynamics by making the feedback signal current decay over time during the feedback cycle. The current starts at full magnitude to ensure adequate charge transfer but decays to a lower level by the end of the cycle, reducing sensitivity to clock jitter. This time-varying current profile resolves the contradiction between maintaining charge transfer accuracy and reducing clock jitter sensitivity.
2Reliability
If a capacitor-based DAC with decreasing current is used, then clock jitter sensitivity is reduced, but high peak currents increase DC power consumption and impose high gain-bandwidth requirements
Solution Approach 1:
The patent applies parameter changes by controlling the feedback signal current to decay from a moderate peak value to a lower residual value during the feedback cycle. This controlled parameter variation allows the system to achieve clock jitter insensitivity while limiting the peak current magnitude, thereby reducing DC power consumption and gain-bandwidth requirements compared to conventional capacitor-based DACs that tolerate high peak currents.
3Measurement precision
If feedback signal current is maintained at full magnitude throughout the cycle, then charge transfer is consistent, but any clock jitter substantially increases or decreases the total charge transferred
Solution Approach 1:
The patent resolves this contradiction by implementing a dynamic current profile where the feedback signal current decays over time during the feedback cycle. The current starts at full magnitude to ensure adequate charge transfer capability but decays to a lower level by the end of the cycle. This time-varying behavior ensures that even if clock jitter occurs, the impact on total charge transferred is minimized because the current is already decaying and less sensitive to timing variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved clock jitter insensitivity and reduced DC current consumption, allowing for lower gain-bandwidth and slew-rate requirements, leading to more efficient and accurate digital conversion in sigma-delta ADCs.
Implementation Method 1
a capacitor circuit configured to be pre-charged to a reference voltage for each feedback cycle of the ADC
Implementation Method 2
a resistive circuit for transferring charge between the capacitor circuit and a loop filter of the ADC in each feedback cycle. The resistive circuit is configured to vary its resistance during each feedback cycle
Data Source
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AI summary
A method and apparatus taught herein provide a digital-to-analog converter (DAC) for use in a conversion feedback path of a sigma-delta type analog-to-digital converter (ADC). The DAC uses current pulse shaping to generate a conversion feedback signal in each feedback cycle of the ADC that provides a consistent charge transfer for accurate digital conversion and has a controlled current pulse shape. In one or more embodiments, the DAC includes a capacitor circuit for charge storage and transfer and a (series) resistive circuit having variable resistance for current pulse shape control. In at least one embodiment, current pulse control limits a peak current of the conversion feedback signal, thereby reducing DC power consumption and gain-bandwidth (GBW) and slew rate requirements of the ADC's integration amplifier, and limiting residual (ending) current in each feedback cycle, which yields commensurate gains in (feedback cycle) clock jitter insensitivity.