Feedback DAC Element Ordering for Higher Sigma-Delta ADC SNDR
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Solution Overview
Problem
Sigma-Delta Analog-to-Digital Converters (ADCs) face significant nonlinearity due to feedback from Digital-to-Analog Converters (DACs), leading to limited system performance, with existing solutions increasing power consumption, noise floor, or degrading loop stability.
Innovation Solution
Optimizing the ordering of DAC elements by determining the optimal sequence through a series of analog-to-digital conversions and storing this ordering in a lookup table to minimize cumulative offset currents, thereby improving Signal-to-Noise plus Distortion Ratio (SNDR) without affecting control loop stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If feedback DAC is used in Sigma-Delta ADC, then digital output can be converted back to analog form for comparison, but significant nonlinearity is introduced that limits system performance
Solution Approach 1:
The patent changes the ordering parameters of DAC unit elements to optimize linearity. By systematically permuting and selecting the best ordering sequence of unit elements, the cumulative offset errors are minimized, improving the overall linearity of the feedback DAC without changing the fundamental feedback conversion mechanism.
2Measurement precision
If existing solutions are applied to reduce nonlinearity, then linearity improves, but power consumption increases
Solution Approach 1:
The patent performs preliminary characterization of DAC unit element offsets during manufacturing testing. The optimal ordering sequence is determined in advance and stored in a lookup table, eliminating the need for real-time calculations or additional active correction circuits that would consume power during normal operation.
3Measurement precision
If existing solutions are applied to reduce nonlinearity, then linearity improves, but noise floor increases
Solution Approach 1:
The patent optimizes the ordering parameters of DAC unit elements to minimize cumulative offset errors. This parameter optimization reduces distortion components that would otherwise appear as noise in the signal band, thereby lowering the effective noise floor while improving linearity.
4Measurement precision
If existing solutions are applied to reduce nonlinearity, then linearity improves, but loop stability degrades
Solution Approach 1:
The patent determines the optimal unit element ordering in advance during manufacturing and stores it in a lookup table. This preliminary action allows the system to use the pre-optimized ordering without requiring real-time adjustments or additional feedback mechanisms that could destabilize the control loop.
5Measurement precision
If DAC unit element ordering is optimized, then SNDR improves by up to 15 dB, but additional testing and lookup table storage are required
Solution Approach 1:
The patent performs the complex optimization work during manufacturing testing rather than during product operation. The lookup table storing optimal ordering sequences requires minimal additional storage and can be implemented using standard memory elements, making the manufacturing complexity acceptable in exchange for significant performance improvement.
Data Source
AI summary
A method for Signal-to-Noise and Distortion Ratio (SNDR) improvement through optimal Digital-to-Analog-Converter (DAC) element selection includes randomizing an order of a plurality of unit elements of a DAC, wherein each of the unit elements is controlled by a respective one of a plurality of digital inputs of the DAC. The plurality of digital inputs is sequentially asserted over at least a subset of a full set of the digital inputs to generate a plurality of analog values of an output of the DAC. A first SNDR of the DAC is measured from the plurality of analog values. A maximum SNDR, corresponding to an optimal order, is determined from the first SNDR and at least one previously measured SNDR. The optimal order of the unit elements of the DAC is stored in a memory to define connections between the digital inputs and the respective unit elements based on the optimal order.