Feedback DAC Timing Mismatch Calibration in Delta-Sigma ADCs
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Solution Overview
Problem
Analog-to-digital converters (ADCs) face challenges in accurately measuring and correcting timing mismatch errors in feedback digital-to-analog converters (DACs), which lead to harmonic distortions and deteriorate Signal-to-Noise-and-Distortion Ratio (SNDR) and spurious free dynamic range (SFDR) performance, especially in high-speed continuous-time delta sigma modulators.
Innovation Solution
A digital measurement technique using cross-correlation between DAC unit elements' output and the entire modulator output to estimate timing mismatch errors, with errors stored in a look-up table for digital or analog correction, employing a pseudo random dither signal to reveal timing mismatch information and a ratio-based estimation method for accurate calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional measurement techniques are used for DAC timing mismatch errors, then the measurement process becomes complex and time-consuming, but the measurement precision and reliability remain insufficient
Solution Approach 1:
The patent introduces a pseudo-random dither signal as an intermediary to facilitate the measurement of timing mismatch errors. This dither signal is injected into the feedback DAC and its effect is observed at the modulator output, enabling the extraction of timing error information through cross-correlation without requiring direct measurement of the timing skew itself. This intermediary approach simplifies the measurement system while improving precision.
Solution Approach 2:
The measurement technique utilizes the existing feedback loop in the delta-sigma modulator to propagate the dither signal through the feedback DAC and back to the output. By analyzing the correlated components at the output, the system can extract timing mismatch information using the feedback path already present in the converter architecture, avoiding the need for additional complex measurement equipment.
2Reliability
If background correlation techniques are used to estimate DAC errors, then static and dynamic mismatches can be determined, but the technique is time-consuming and complex to implement
Solution Approach 1:
The patent performs the timing mismatch error measurement during the normal operation of the ADC using the existing feedback loop, rather than requiring a separate calibration phase. The pseudo-random dither signal is continuously injected and correlated, allowing real-time estimation of timing errors without stopping the conversion process or adding significant overhead time.
Solution Approach 2:
The measurement system utilizes the ADC's own feedback loop and output signal to perform the timing error measurement. The dither signal injected into the feedback DAC naturally propagates through the system and appears at the output, where it can be correlated with the original dither to extract timing information. This self-service approach eliminates the need for external test equipment or separate measurement channels.
3Ease of manufacture
If timing mismatch errors are not corrected, then the ADC can operate without additional complexity, but harmonic distortions occur and SNDR and SFDR performance deteriorate
Solution Approach 1:
The patent uses the feedback loop to continuously measure timing mismatch errors and enables digital correction of these errors. The measured timing error information is used to adjust the feedback DAC operation, compensating for the timing skew and eliminating the resulting harmonic distortions. This feedback-based correction maintains signal integrity without requiring complete redesign of the converter architecture.
Data Source
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AI summary
For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine timing mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology utilizes cross-correlation of each DAC unit elements (UEs) output to the entire modulator output to measure its timing mismatch error respectively. Specifically, the timing mismatch error is estimated using a ratio based on a peak value and a value for the next tap in the cross-correlation function. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.