Feedback-Controlled Delay Line for Process-Insensitive Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional delay lines in electronic devices are susceptible to significant variations due to process and environmental factors, leading to uncertainties in delay times, which forces designers to over-design circuits and devices to accommodate these inconsistencies, resulting in reduced performance and increased noise patterns.
Innovation Solution
A process-insensitive delay line that adjusts delay time through a digitally controlled ratio of charging and control currents, using a voltage-controlled delay unit and phase detector to maintain consistent delay times despite variations, ensuring accurate timing in applications like CMOS imagers and ADCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional delay lines using series inverters are used to accommodate fabrication differences, then delay time can be adjusted to match required timing, but delay time varies by up to fifty percent due to process and environmental variations
Solution Approach 1:
The patent employs a feedback mechanism where the delay line output is fed back to adjust the control voltage, creating a self-correcting system that compensates for process and environmental variations. The feedback loop continuously monitors the actual delay and adjusts the control parameter to maintain the target delay time despite variations in fabrication or operating conditions.
Solution Approach 2:
The patent changes the control parameter from fixed physical dimensions (inverter sizes) to a dynamically adjustable electrical parameter (control voltage). This allows the delay line to compensate for variations by adjusting the control voltage to counteract the effects of process corners, temperature changes, and power supply fluctuations, thereby maintaining consistent delay time.
2Reliability
If design margins are added to accommodate delay variations, then reliability is improved, but circuit performance is reduced due to over-design
Solution Approach 1:
The feedback mechanism eliminates the need for conservative design margins by actively compensating for delay variations in real-time. Instead of adding static time margins that reduce circuit throughput, the system dynamically adjusts the delay to match the actual conditions, maintaining both reliability and optimal performance.
Solution Approach 2:
The patent transitions from static delay lines with fixed characteristics to dynamic delay lines that can adapt their delay time based on actual operating conditions. This dynamic adjustment capability allows the system to maintain precise timing without requiring excessive design margins, thereby preserving circuit performance and productivity.
3Manufacturing precision
If design margins are added to ensure timing accuracy, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent achieves high timing accuracy by adjusting electrical parameters (control voltage) rather than adding physical complexity. The delay line uses variable gain amplifiers and controlled current sources that can be tuned to compensate for variations, providing precise timing control without requiring additional circuit stages or complex interconnections.
Data Source
AI summary
A delay line including a phase detector having two inputs and one output. The first input of the phase detector is connected to an input of the delay line. The second input of the phase detector is connected to an output of the delay line. The output of the phase detector is connected to a control circuit which controls current flow at a control node to produce a control voltage at the node. A voltage-controlled delay unit is responsible to the control voltage to control a delay applied to a signal at an input of the delay line.