Logic-in-Memory Inverter Using Feedback FET
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Solution Overview
Problem
Conventional CMOS-based logic-in-memory technology faces challenges with high power consumption, increased area requirements, and instability due to the separation of processor and memory layers, limiting data processing speed and integration density in von Neumann-based systems, especially in data-intensive applications like 5G communication and AI.
Innovation Solution
A logic-in-memory inverter using a positive feedback loop of a feedback field-effect transistor and a metal oxide semiconductor field-effect transistor, integrated within a CMOS process, which controls potential barriers and generates a positive feedback loop to perform logical operations and memory functions, reducing power consumption and improving integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional CMOS-based LIM technology configures a logic circuit with numerous transistors to implement logic-in memory function, then the logic-in memory function is achieved, but the overall area is greatly increased and power consumption increases
Solution Approach 1:
The patent combines the logic circuit function and memory function into a single integrated structure using only two transistors. The feedback field-effect transistor simultaneously performs logic inversion and data storage functions, eliminating the need for separate logic circuits and memory cells, thereby achieving logic-in-memory operation with reduced transistor count, area, and power consumption
Solution Approach 2:
The feedback field-effect transistor is designed to perform multiple functions: it acts as both the inverting element and the storage element. By utilizing the feedback loop mechanism, the same transistor structure enables both logic operation and data retention, making the device universal and eliminating the need for dedicated logic and memory components
2Adaptability or versatility
If conventional CMOS-based LIM technology configures a logic circuit with numerous transistors to implement logic-in memory function, then the logic-in memory function is achieved, but the overall area is greatly increased
Solution Approach 1:
The patent merges the logic circuit function and memory function into a single integrated structure using only two transistors. The feedback field-effect transistor simultaneously performs logic inversion and data storage functions, eliminating the need for separate logic circuits and memory cells, thereby achieving logic-in-memory operation with reduced transistor count, area, and power consumption
Solution Approach 2:
The patent divides the conventional separate logic and memory structures into a unified compact cell. By segmenting the functions at the transistor level rather than at the circuit block level, the design achieves high integration density while maintaining full logic-in-memory functionality
3Ease of manufacture
If processor and memory are separated to transmit data through a bus in von Neumann-based system, then the system architecture is established, but data transmission delay time and power consumption increase
Solution Approach 1:
The patent merges the processor and memory functions into a single integrated device at the transistor level. By combining the logic inversion function and data storage function in the same feedback field-effect transistor, the design eliminates the physical separation between processor and memory, thereby removing the need for data transmission through buses and significantly reducing data transmission delay time and power consumption
4Ease of manufacture
If processor and memory are separated to transmit data through a bus in von Neumann-based system, then the system architecture is established, but power consumption increases
Solution Approach 1:
The patent merges the processor and memory functions into a single integrated device at the transistor level. By combining the logic inversion function and data storage function in the same feedback field-effect transistor, the design eliminates the physical separation between processor and memory, thereby removing the need for data transmission through buses and significantly reducing data transmission delay time and power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables low-power, high-integration density logic-in-memory operations with improved processing speed, reducing standby power and enabling parallel data processing methods in fields like pattern recognition and image analysis without external bias, while maintaining logic states through the feedback loop mechanism.
Implementation Method 1
When an input voltage VIN switches from a low level to a zero level, a height of a potential barrier in a channel region of the feedback field-effect transistor may block electrons and holes injected into the channel region from a drain region and a source region
Implementation Method 2
when the input voltage VIN is at a high level, a positive feedback loop in which electrons and holes are injected into a channel region from a drain region and a source region of the nanostructure may be generated
Data Source
AI summary
Disclosed is technology that is driven using a positive feedback loop of a feedback field-effect transistor and is capable of performing a logic-in memory function. The logic-in-memory inverter includes a metal oxide semiconductor field-effect transistor, and a feedback field-effect transistor in which a drain region of a nanostructure is connected in series to a drain region of the metal oxide semiconductor field-effect transistor, wherein the logic-in-memory inverter performs a logical operation is performed based on an output voltage VOUT that changes depending on a level of an input voltage VIN that is input to a gate electrode of the feedback field-effect transistor and a gate electrode of the metal oxide semiconductor field-effect transistor while a source voltage VSS is input to a source region of the nanostructure and a drain voltage VDD is input to a source region of the metal oxide semiconductor field-effect transistor.