Feedback Field-Effect Array Device for Volatile Non-Volatile Memory Integration

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Solution Overview

Problem

Conventional memory devices face challenges in integrating capacitorless DRAM and flash memory in a single cell due to data disturbance during volatile operations and structural incompatibilities between volatile and non-volatile memory devices, leading to inefficiencies in power consumption and read sensing margins.

Innovation Solution

An array circuit using feedback field-effect electronic devices with a diode structure, including conductivity-type regions, an intrinsic region, a barrier region, a tunnel oxide layer, a charge storage layer, and a block oxide layer, capable of switching between volatile and non-volatile operations with low power consumption and high efficiency, by applying specific gate and drain voltages to store and retrieve data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If capacitorless DRAM and flash memory are integrated in a single cell, then miniaturization and integration are achieved, but data disturbance occurs during volatile memory operations

Engineering Contradiction:
Improvecell sizeVSAvoiddata stability
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The memory cell is segmented into distinct functional regions: a volatile memory portion (capacitorless DRAM with access transistor and storage node) and a non-volatile memory portion (flash memory with charge storage layer). This segmentation allows each portion to operate independently, preventing data disturbance in one portion from affecting the other, while achieving miniaturization through integration in a single cell structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A separation structure (such as a dielectric layer or isolation region) is introduced as an intermediary between the volatile and non-volatile memory portions. This intermediary prevents charge leakage and data disturbance from the volatile portion from affecting the stored data in the non-volatile portion, while still allowing both memory types to coexist in a single integrated cell

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If conventional volatile DRAM and non-volatile flash memory devices are used separately, then each device has optimized structure for its characteristics, but structural incompatibility prevents flexible use when volatile or non-volatile operation characteristics are selectively required

Engineering Contradiction:
Improvedevice optimizationVSAvoidoperation mode flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The memory device is designed with universal functionality by integrating both volatile and non-volatile memory portions in a single cell structure. The device can operate in volatile memory mode (using the capacitorless DRAM portion), non-volatile memory mode (using the flash memory portion), or a hybrid mode (using both portions together), providing operational flexibility while maintaining optimized structures for each memory type

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If complex operation methods are adopted in FBFETs due to charge trap spacers or dual gates, then electrical/physical/structural properties are improved, but device complexity increases

Engineering Contradiction:
Improveelectrical propertiesVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention extracts and removes the complex components (charge trap spacers and dual gate structures) from the FBFET design. Instead, it uses a simplified single-gate structure with strategically positioned source and drain regions that achieve the desired electrical properties through geometric configuration and doping profiles, rather than through complex additional structures

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables efficient miniaturization and integration of memory devices with reduced leakage current, fast read operations, and low power consumption, while preventing short channel effects and requiring minimal voltage for writing and erasing, thus enhancing overall system performance.

Implementation Method 1

a charge storage layer (130) disposed on the tunnel oxide layer and storing electric charge of current introduced from the diode structure

Methodology Applied
Scientific EffectCharge storage: Electrical Accumulator

Implementation Method 2

a tunnel oxide layer (120) disposed so as to surround the barrier region (116) and the intrinsic region (114)

Methodology Applied
Scientific EffectTunneling:

Data Source

PatentUS10643699B2Feedback field-effect array device capable of converting between volatile and non-volatile operations and array circuit using the same
Publication Date: 2020.05.05 KOREA UNIV RES & BUSINESS FOUND
  • US10643699B2 patent drawing
  • US10643699B2 patent drawing
  • US10643699B2 patent drawing

AI summary

The present disclosure discloses a feedback field-effect array device capable of converting between volatile and non-volatile operations and an array circuit using the same. According to one embodiment of the present disclosure, the array circuit may include a plurality of feedback field-effect array devices, wherein the source region of the feedback field-effect electronic device and the drain region of an access electronic device may be connected to each other in series, the feedback field-effect electronic device may be connected to a bit line and a first word line, the access electronic device may be connected to a source line and a second word line, and any one of first and second gate voltages may be applied to the first word line to store data in a first logic state or data in a second logic state.