Feedback Field-Effect Device for High-Speed Memory with Low Leakage
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Solution Overview
Problem
Conventional memory devices face challenges such as slow operation speed, high power consumption, interference between memory cells, and sneak current issues, particularly in the context of Internet of Things applications, where high-speed and low-power memory solutions are required. Additionally, existing devices like DRAM and SRAM have limitations in integration and leakage current, and thyristor-based devices suffer from mutual disturbance due to parallel word line arrangements.
Innovation Solution
A feedback field-effect electronic device with a p-n-i-n transistor and an access transistor connected in series, which selectively applies voltage to a bit line and two word lines to implement a feedback loop memory mechanism, preventing interference and sneak current through access transistors and improving switching characteristics and subthreshold swing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If DRAM memory device is used, then high degree of integration is achieved, but operation speed becomes slow and power consumption increases due to periodic refresh
Solution Approach 1:
The memory device is segmented into distinct functional regions: a first region with a first doped concentration and a second region with a second doped concentration. This segmentation allows different parts of the device to be optimized for different functions - one region for high-speed operation and another for low-power consumption, thereby resolving the contradiction between operation speed and power consumption while maintaining high integration density.
2Speed
If SRAM memory device is used, then high-speed operation is achieved, but degree of integration is low and leakage current increases
Solution Approach 1:
Different regions of the memory device are assigned different doped concentrations to optimize local properties. The first region with the first doped concentration is optimized for high-speed operation similar to SRAM, while the second region with the second doped concentration is optimized for low leakage current and high integration density. This local quality differentiation allows the device to achieve both high-speed operation and high integration density simultaneously.
3Device complexity
If thyristor-based device with parallel word lines is used, then array configuration is simplified, but mutual disturbance occurs between word lines
Solution Approach 1:
The invention extracts and eliminates the source of mutual disturbance by using perpendicular word line arrangements instead of parallel arrangements. The first word line and second word line are arranged perpendicular to each other, which removes the coupling effect that causes mutual disturbance in parallel arrangements. This maintains array configuration simplicity while eliminating the reliability issue of word line interference.
4Area of stationary object
If MOSFET-based memory device is miniaturized, then integration density increases, but subthreshold swing increases and leakage current increases
Solution Approach 1:
The invention changes the doping concentration parameter to resolve the contradiction. By using different doped concentrations in different regions, the device maintains effective subthreshold swing characteristics even when miniaturized. The specific doped concentrations are optimized to prevent subthreshold swing degradation and leakage current increase that typically occur with miniaturization, thereby achieving high integration density without the usual penalty of increased leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed memory operations with reduced leakage current, improved switching characteristics, and lower operating voltage, while preventing mutual disturbance between word lines, thus enhancing retention capacity and power efficiency.
Implementation Method 1
feedback field-effect electronic device using a feedback loop operation, capable of implementing a feedback loop memory mechanism by selectively applying voltage to a bit line and two word lines
Implementation Method 2
when a gate voltage is applied through the first and second word lines, and the voltage magnitude of the bit line is greater than a reference voltage, the diode structure may store data in a first logic state, and when the voltage magnitude of the bit line is less than a reference voltage, the diode structure may store data in a second logic state
Data Source
AI summary
The present disclosure discloses a feedback field-effect electronic device using a feedback loop operation and an array circuit using the feedback field-effect electronic device. According to one embodiment of the present disclosure, the array circuit includes a plurality of feedback field-effect electronic devices in which the source region of a diode structure and the drain region of an access electronic device are connected in series, wherein the diode structure is connected to a bit line and a first word line, the access electronic device is connected to a source line and a second word line, and a random access operation is performed by selectively applying voltage to the bit line and the first and second word lines.