Self-Gating Pulsed Flip-Flop With Feedback-Based Clock Suppression
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Solution Overview
Problem
Conventional synchronous circuits, including master-slave flip-flops and pulsed latches, consume significant dynamic power due to clock signal charging and discharging, and existing power reduction techniques like clock gating are not effective in all design portions, particularly where large groups of flip-flops cannot be grouped to respond to a shared register enable signal.
Innovation Solution
A self-gating pulsed flip-flop circuit that generates a pulsed clock signal based on an input clock signal, input data signal, and a feedback signal indicative of the stored state, using a comparator and set-reset latch to control the pulse enable signal, thereby reducing dynamic power consumption by preventing clock signal propagation when no state update is needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If clock gating is used to reduce dynamic power consumption, then power consumption decreases, but the technique is not effective in portions of design where large groups of flip-flops cannot be grouped to respond to a shared register enable signal
Solution Approach 1:
The invention divides the clock gating control into individual flip-flop level operations rather than requiring large grouped operations. Each flip-flop has its own pulse generator that independently generates pulsed clock signals based on local data changes, eliminating the need to group flip-flops into large blocks for power savings to be achieved.
Solution Approach 2:
Each flip-flop in the invention is self-sufficient in generating its own clock pulse timing. The pulse generator within each flip-flop automatically detects data changes and generates appropriate clock pulses without requiring external group-level control signals, making the power reduction technique universally applicable across all design portions.
2Loss of energy
If pulsed latch is used instead of master-slave flip-flop, then power consumption reduces, but there is no mechanism to guarantee capture of input data before the fall of pulsed clock signal
Solution Approach 1:
The invention uses feedback signals from the latch output to control the pulse generator. The pulse generator monitors the latch state and generates clock pulses only when data changes are detected, ensuring that data is properly captured before the pulsed clock signal falls. This feedback mechanism guarantees reliable data capture while maintaining power reduction benefits.
Solution Approach 2:
The pulse generator in the invention performs preliminary detection of data changes before generating the clock pulse. By detecting data transitions in advance and generating appropriately timed pulses, the system ensures data is ready for capture before the clock signal activates, preventing write failures and hold time violations.
3Reliability
If conventional master-slave flip-flop is used, then data storage is reliable, but substantial dynamic power is consumed due to clock signal charging and discharging capacitances
Solution Approach 1:
The invention replaces the continuous clocking mechanism of master-slave flip-flops with periodic pulsed clock signals. The pulse generator creates brief, periodic clock pulses only when data changes occur, rather than continuously charging and discharging capacitances with every clock cycle. This periodic action maintains data storage reliability while dramatically reducing dynamic power consumption in circuits with infrequent state changes.
Data Source
AI summary
A circuit includes a latch configured to update a stored state of the latch in response to an input data signal and a pulsed clock signal. The circuit includes a pulse generator configured to generate the pulsed clock signal based on an input clock signal, the input data signal, and a feedback signal indicative of a stored state of the latch. The pulse generator may be configured to generate a pulse enable signal based on the input data signal, the input clock signal, and the feedback signal. The pulsed clock signal may be based on the pulse enable signal and the input clock signal. The pulse generator may generate the pulsed clock signal to have a pulse of a first signal level in response to an indication that the stored state of the latch needs to change and generates the pulsed clock signal to have a second signal level, otherwise.