Feedback-Guided High-Level Synthesis Scheduling
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Solution Overview
Problem
Existing high-level synthesis (HLS) tools struggle to accurately model optimizations in downstream tools, leading to insufficient and ineffective scheduling results due to the lack of low-level feedback.
Innovation Solution
The iterative system of difference constraints (ISDC) approach is employed, which leverages low-level feedback from downstream tools like logic synthesizers to iteratively refine HLS scheduling. This involves extracting subgraphs, passing them to downstream tools for logic synthesis, and using the feedback to recalculate delay estimations and prune redundant constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pre-characterized delay estimation is used in isolation for scheduling, then timing analysis can be performed at high-level, but the scheduling results are insufficient and ineffective due to not modeling downstream tool optimizations
Solution Approach 1:
The patent implements a feedback mechanism where downstream tools (logic synthesizer, placement tool, routing tool) provide actual timing analysis results back to the scheduler. This feedback loop allows the scheduler to iteratively refine delay estimates based on real downstream tool performance rather than relying solely on pre-characterized isolated operation delays, thereby improving both measurement precision and scheduling result reliability
Solution Approach 2:
The scheduler performs preliminary scheduling using initial delay estimates, then systematically extracts subgraphs and passes them to downstream tools for actual timing analysis. This preliminary action followed by refinement allows the system to capture downstream tool optimizations while maintaining scheduling efficiency
2Reliability
If iterative refinement with downstream tool feedback is implemented, then scheduling result quality is improved, but computational complexity and tool integration requirements increase
Solution Approach 1:
The patent segments the computation graph into subgraphs that can be independently processed by downstream tools. This segmentation allows the complex iterative refinement process to be broken down into manageable pieces, reducing the overall system complexity while maintaining the benefits of feedback-driven scheduling optimization
Solution Approach 2:
The patent introduces an intermediary layer that manages the interaction between the scheduler and downstream tools. This intermediary handles the extraction of subgraphs, coordination of timing analysis, and integration of feedback results, thereby managing system complexity while enabling iterative refinement
Data Source
AI summary
The technology employs an iterative system of difference constraints (ISDC) approach that leverages low-level feedback from downstream tools to iteratively refine scheduling with respect to circuit design high-level synthesis. In each iteration, a number of subgraphs are extracted from an original computation graph and passed to selected downstream tools, e.g., for logic synthesis, placement and/or routing. The downstream tools' compilation results are extracted and fed back to a scheduler. With the feedback, the scheduler recalculates delay estimation between each pair of nodes in the original computation graph and prunes redundant scheduling constraints. As a result, the explorable design space is enlarged in the next iteration, leading to refined scheduling results. This feedback-guided approach is compatible with versatile design constraints and objectives, such as minimizing register usage given a targeted clock period, minimizing the clock period given a constrained area budget, etc., to provide improvements to the system operation.