Feedback Latch Circuit Layout for Scan Hold-Margin
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Solution Overview
Problem
Existing scan latches face issues with insufficient hold-margin when used in a master/slave configuration during scan mode, leading to potential hold violations, and require a more area-efficient design.
Innovation Solution
A compact scan latch design incorporating a MOS device with a first latch configured to receive a latch input and clock, outputting a function of the latch feedback, which is slower than typical latches to address hold-margin issues and feature an area-efficient layout by using a series of transistors and specific gate configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional scan latch is used in a master/slave configuration with a functional latch, then the latch can operate in scan mode, but the functional latch has an insufficient hold-margin leading to hold violations
Solution Approach 1:
The latch is divided into two separate latches (master scan latch and slave functional latch) with distinct transistor sets and control logic. Each latch handles specific functions independently, allowing optimization of hold-margin in the functional latch while maintaining scan functionality in the master latch, thereby resolving the hold-violation issue without excessive complexity
Solution Approach 2:
The latch configuration dynamically switches between scan mode and functional mode through clock signal control. The master latch operates during scan mode while the slave latch operates during functional mode, enabling the system to adapt its behavior based on operational requirements and avoid hold-margin violations in each mode
2Area of moving object
If a conventional scan latch design is used, then the latch can perform scanning function, but it occupies more area than necessary
Solution Approach 1:
The scan latch and functional latch are merged into a single integrated circuit block sharing common transistors (T14-T16, T22-T24) and control logic. This consolidation reduces the total area required compared to separate implementations while maintaining both scan and functional operation capabilities through mode-dependent activation
Solution Approach 2:
The latch circuit is designed to perform multiple functions: it operates as a scan latch during test mode and as a functional latch during normal operation. The same physical structure supports both modes through clock signal control, eliminating the need for separate dedicated circuits and thereby reducing area while preserving versatility
Data Source
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AI summary
A MOS device includes a first latch configured with one latch feedback F and configured to receive a latch input I and a latch clock C. The first latch is configured to output Q, where the output Q is a function of CF, IF, and IĈ, and the latch feedback F is a function of the output Q. The first latch may include a first set of transistors stacked in series in which the first set of transistors includes at least five transistors. The MOS device may further include a second latch coupled to the first latch. The second latch may be configured as a latch in a scan mode and as a pulse latch in a functional mode. The first latch may operate as a master latch and the second latch may operate as a slave latch during the scan mode.