Feedback Level Shifter for Low-Current Fast Voltage Transfer

The patent employs periodic action by using pulsed gate signals to activate the PMOS transistor only during the brief moment when level shifting is required. The transistor is switched on momentarily to transfer the low-voltage signal to the high-voltage domain, then switched off to eliminate continuous current flow through the resistor, thereby reducing quiescent current while maintaining the level shifting function.

The patent applies preliminary action by pre-charging the gate of the PMOS transistor through a dedicated charging path before the actual signal transfer occurs. This ensures the transistor is ready to conduct immediately when needed, while the gate remains isolated during idle periods through discharge paths, preventing continuous current consumption.

The patent resolves this contradiction by using periodic gating - the PMOS transistor is activated only during brief intervals when signal transfer is needed. During these short pulses, a small resistor value can be used to achieve fast switching without concern for continuous current consumption, as the transistor is off during idle periods, eliminating quiescent current entirely.

The patent applies dynamics by making the gate resistance time-variable through the switching action. During the active switching period, the effective resistance is low to enable fast transitions. During idle periods, the gate is disconnected or high-impedance, making the effective resistance very high, thereby eliminating continuous current flow while maintaining fast switching capability when needed.

The patent extracts and eliminates the problematic cross-conduction path inherent in cross-coupled level shifters. Instead of using the conventional cross-coupled configuration where both transistors can conduct simultaneously causing large losses, this patent uses a single PMOS transistor controlled by pulsed gate signals, removing the cross-conduction mechanism entirely while preserving the level shifting function.

The patent uses periodic gating to ensure that the PMOS transistor conducts only during brief, controlled intervals when signal transfer is required. This pulsed operation prevents continuous or simultaneous conduction paths that would cause cross-conduction losses, as the transistor is fully off during idle periods and the gate is isolated from both voltage domains when not actively switching.