Feedback Shift-Register BIST Using Segmented Controllable Cells
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Solution Overview
Problem
Traditional Built-In Self-Test (BIST) designs for cryptographic systems based on Feedback Shift-Registers (FSRs) face issues with increased propagation delay and high dynamic power dissipation due to scan design, leading to reduced data rates and prolonged testing times, which can result in incorrect fault detection and overheating.
Innovation Solution
The implementation of a BIST method for FSRs that uses controllable cells with multiplexers to select either a predecessor cell or a test value as input, allowing for testing of combinational logic, reducing propagation delay and dynamic power dissipation, and utilizing a minimal test set to detect faults efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan design is used for BIST, then fault detection capability is improved, but propagation delay increases
Solution Approach 1:
The invention divides the FSR cells into two distinct types: controllable cells (with MUX for test pattern loading) and observable cells (for fault detection). This segmentation allows independent optimization of test access and normal operation paths, resolving the contradiction between fault detection capability and propagation delay by eliminating MUX from the critical data path.
Solution Approach 2:
The invention introduces an intermediary mechanism where controllable cells act as test pattern sources and observable cells act as fault detection sensors. This intermediary structure enables fault detection without requiring scan chains, thereby avoiding the propagation delay penalty while maintaining comprehensive fault coverage.
2Reliability
If pseudo-random sequences are used as test patterns, then fault coverage is improved, but testing time increases
Solution Approach 1:
The invention applies preliminary action by pre-defining a minimal complete test set based on the dependence sets of feedback functions. This allows the test patterns to be systematically generated and applied without requiring extensive pseudo-random sequences, significantly reducing testing time while maintaining complete fault coverage through targeted test vectors.
3Reliability
If pseudo-random sequences are used as test patterns, then fault coverage is improved, but dynamic power dissipation increases
Solution Approach 1:
The invention applies partial action by using only the minimal necessary test patterns required to cover all faults, rather than applying extensive pseudo-random sequences. This reduces the number of switching events in the circuit, thereby reducing dynamic power dissipation while still achieving complete fault coverage through the strategically designed minimal test set.
4Ease of operation
If scan design is used for BIST, then testability is improved, but data rate decreases
Solution Approach 1:
The invention segments the circuit into controllable and observable cells with dedicated functionality. Controllable cells handle test pattern loading while observable cells handle fault detection, and this segmentation eliminates the need for MUX in the critical path, thereby maintaining the original high data rate while improving testability through systematic test pattern application.
Data Source
AI summary
A Feedback Shift-Register (FSR) enabling improved testing, e.g., Built-In Self-Tests (BIST), is provided. Each cell of the FSR may either be an observable cell, associated with a non-trivial feedback function implemented by a combinational logic circuit, or a controllable cell, having an associated state variable which belongs to the dependence set of exactly one of the non-trivial feedback functions. Each controllable cell is provided with a multiplexer for selecting either a predecessor cell of the controllable cell or a test value as input. Thus, the sequential circuit of the FSR in an embodiment is tested using tests for combinational logic. The disclosed test procedures utilize a minimal set of test vectors and allow detection of all single stuck-at faults in the FSR. The resulting dynamic power dissipation during test can be considerably less than known BIST designs.