Feedback VGIDL Voltage Circuit for Stable GIDL Control
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in controlling gate-induced drain leakage (GIDL) current, which is sensitive to temperature-dependent power supply voltages and has limitations in pull-up and pull-down driving abilities, leading to variations across temperature and process corners.
Innovation Solution
A VGIDL circuit is designed with a feedback loop configuration that includes biasing stages, a VGIDL generation stage, and a feedback stage, using variable resistors and transistors to generate a voltage (VGIDL) that is insensitive to temperature variations and has enhanced pull-up and pull-down driving capabilities, allowing for faster ramp-up times and adjustable voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional voltage generation circuits are used, then the circuit structure is simple, but the GIDL current control is poor due to temperature-dependent power supply voltages and limited pull-up/pull-down driving abilities
Solution Approach 1:
The patent implements a feedback mechanism where the voltage generation circuit monitors its own output voltage and adjusts the gate voltage of the transistor accordingly. The feedback loop compares the actual output voltage with the desired voltage level and dynamically modifies the gate voltage to maintain precise control over GIDL current, resolving the contradiction between simple structure and reliable control.
Solution Approach 2:
The circuit dynamically adjusts the gate voltage of the transistor based on real-time conditions to optimize GIDL current control. By making the gate voltage variable rather than fixed, the circuit adapts to temperature changes and loading conditions, improving control reliability without requiring a completely complex circuit architecture.
2Object-generated harmful factors
If the gate voltage is increased to control GIDL current, then the GIDL current is reduced, but the transistor threshold voltage limits the maximum achievable voltage
Solution Approach 1:
The patent introduces an intermediary voltage generation stage that produces an intermediate voltage, which is then used to drive the gate of the transistor. This intermediary voltage can exceed the transistor threshold voltage limitation, allowing the gate to achieve higher voltages necessary for effective GIDL current control while the intermediary circuit handles the voltage multiplication or boosting function.
Solution Approach 2:
The circuit transitions from a single-voltage-dimension approach to a multi-stage voltage generation approach, where an intermediate voltage dimension is created. This allows the system to achieve gate voltages beyond the transistor threshold by composing multiple voltage stages, expanding the adaptable voltage range for GIDL control.
3Speed
If the pull-up and pull-down driving abilities are enhanced, then the voltage ramp-up time is reduced, but the bias current and cross current increase
Solution Approach 1:
The circuit dynamically adjusts the driving strength of the pull-up and pull-down devices based on the required voltage transition speed. During rapid voltage changes, the driving ability is enhanced to reduce ramp-up time. During steady-state operation, the driving strength is reduced to minimize bias and cross currents, achieving a dynamic balance between speed and energy consumption.
Solution Approach 2:
The patent changes the operating parameters of the pull-up and pull-down devices, such as their width-to-length ratios or gate voltages, to optimize the trade-off between driving ability and current consumption. By adjusting these parameters dynamically or through design optimization, the circuit achieves fast voltage transitions when needed while maintaining low static current consumption.
Data Source
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AI summary
Disclosed are apparatuses and methods for controlling gate-induced drain leakage current in a transistor device. An apparatus may include a first biasing circuit stage configured to provide a biasing voltage on a biasing signal line, the biasing voltage based on a current through a first resistor associated with the first biasing circuit stage, a voltage generation circuit stage coupled to the first biasing circuit stage, the voltage generation circuit stage having an output transistor that is coupled to the biasing signal line through a gate terminal of the output transistor, and an output line coupled to the voltage generation circuit stage and configured to provide an output voltage signal having a steady-state voltage that is less than a power supply voltage by an amount that corresponds to a voltage drop across the first resistor associated with the first biasing circuit stage.