Input-Feedforward Delta-Sigma ADC for Low-Power RF Receivers
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Solution Overview
Problem
Conventional delta-sigma loop filters in analog-to-digital converters (ADCs) face design challenges due to stringent gain and timing requirements, leading to increased complexity and power consumption, particularly in low-power RF applications.
Innovation Solution
The implementation of input-feedforward delta-sigma loop filters with fewer gain stages and reduced loading on integrators, along with programmable coefficients for adjustable bandwidth, allows for efficient noise shaping and flexible operation between Zero-IF and Low-IF modes, reducing power consumption and hardware requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional delta-sigma loop filters are used, then noise shaping is achieved, but gain and timing requirements become stringent, increasing device complexity and power consumption
Solution Approach 1:
The loop filter is divided into multiple integrator stages (first integrator, second integrator, third integrator) with distributed gain stages. Each integrator processes a portion of the signal, breaking down the complex filtering operation into manageable segments that individually have relaxed gain and timing requirements compared to a single-stage filter.
Solution Approach 2:
The patent introduces feedforward paths that bypass certain integrator stages, creating additional signal paths through the loop filter. This dimensional expansion in the signal flow graph allows the filter to achieve the required noise shaping transfer function without increasing the gain burden on individual integrator stages, thereby reducing timing constraints and complexity.
2Reliability
If conventional delta-sigma loop filters with multiple gain stages are used, then noise shaping is improved, but power consumption increases
Solution Approach 1:
The patent extracts and removes unnecessary gain stages from the conventional loop filter architecture. By analyzing the noise shaping transfer function requirements, the design eliminates redundant amplification stages while maintaining the essential noise shaping performance, directly reducing the power consumption associated with fewer active components.
Solution Approach 2:
The feedforward paths provide partial filtering action that compensates for the reduced gain stages. By implementing feedforward filtering in parallel with the feedback path, the system achieves adequate noise shaping with less aggressive feedback gain, thereby reducing power consumption while maintaining performance through a combination of partial feedback and feedforward actions.
3Adaptability or versatility
If programmable coefficients are added for adjustable bandwidth, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements programmable coefficients that modify the feedback and feedforward path gains. By changing these coefficients, the bandwidth and noise shaping characteristics of the loop filter can be adjusted to match different modulation schemes and channel conditions. The coefficients are programmed into the gain stages, allowing dynamic reconfiguration without hardware changes.
Solution Approach 2:
The loop filter is designed with a universal architecture that can support multiple communication protocols and bandwidth requirements through software-controlled coefficients. The same physical hardware structure serves multiple functions by reprogramming the gain values, eliminating the need for separate dedicated filters for each application and reducing overall system complexity despite the added programmability.
Data Source
AI summary
Various embodiments relate to an analog-to-digital converter (ADC). The ADC may include a first channel including a first delta-sigma loop filter and a second channel including a second delta-sigma loop filter. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may also include a first summing node having an output coupled to an input of the first integrator, and a feedforward path from an input of the delta sigma loop filter to a first input of the first summing node. Further, each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first feedback path from an output of the quantizer to a second input of the first summing node.