Feedforward Divider PLL for Wide-Range Low-Jitter Clocking
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Solution Overview
Problem
Analog phase locked loops (PLLs) face challenges in reducing the ring VCO frequency range, especially as supply voltage scales below 1.2V, while the demand for wider frequency ranges from a single PLL continues to grow, particularly due to PVT variations.
Innovation Solution
A dual-PLL architecture with dynamically adjustable feedforward divider factors, allowing for a wide frequency range of 500:1, where each sub-PLL has a voltage-controlled oscillator and a feedforward divider circuit, with control circuitry selecting division factors based on output clock signals and voltage inputs to maintain optimal VCO operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If supply voltage is scaled below 1.2V to reduce power consumption, then power efficiency is improved, but the VCO frequency range is reduced
Solution Approach 1:
The patent divides the frequency range requirement into two segments: the VCO generates frequencies within its limited range (due to low voltage constraints), and the feedforward divider handles the frequency multiplication/division to achieve the wide overall frequency range. This segmentation allows the VCO to operate at low voltage while the system still provides wide frequency coverage.
Solution Approach 2:
The feedforward divider acts as an intermediary between the VCO and the output, enabling the system to achieve frequency ranges beyond what the VCO can generate directly. The divider translates the VCO's limited frequency output into the required wide frequency range at the system output level.
2Adaptability or versatility
If a single PLL is used to cover wide frequency range, then frequency versatility is improved, but jitter performance deteriorates
Solution Approach 1:
The patent implements dynamic adjustment of the feedforward divider ratio based on the VCO frequency range. By adaptively changing the division factor, the system optimizes jitter performance for different frequency ranges while maintaining wide overall frequency coverage, rather than using a fixed divider ratio.
Solution Approach 2:
The system changes the divider ratio parameter dynamically according to operating conditions. This parameter adjustment allows the PLL to maintain optimal jitter characteristics across different frequency ranges by selecting appropriate division factors.
3Device complexity
If fixed division factors are used in feedforward divider, then device complexity is reduced, but adaptability to PVT variations worsens
Solution Approach 1:
The patent implements dynamic selection of division factors based on detected PVT conditions. The system monitors process, voltage, and temperature variations and adjusts the feedforward divider ratio accordingly, enabling adaptive compensation for PVT effects without requiring overly complex control circuitry.
Data Source
AI summary
In some embodiments, a chip includes first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors. The chip also includes phase locked loop control circuitry to select the first and second division factors. Other embodiments are described and claimed.