Feedforward Jitter Correction for High-Speed Data Links
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Solution Overview
Problem
Conventional clock-recovery circuits in high-speed data transmission systems suffer from untracked transmitter clock jitter, leading to increased Bit Error Rate (BER) due to limited loop bandwidth in feedback loops, which fail to account for jitter above the loop bandwidth.
Innovation Solution
Implement a feedforward jitter correction mechanism combining closed-loop tracking with open-loop compensation, using a timing error detector to measure sampling offset and a filter to remove jitter through re-sampling, employing a combination of a finite impulse response filter and multi-tap FIR filter for effective jitter extraction and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the feedback loop bandwidth is limited to avoid amplification of transmitter clock jitter, then the stability of the clock recovery circuit is improved, but the measurement precision of sampling jitter is degraded due to untracked high-frequency jitter
Solution Approach 1:
The patent segments the jitter correction function into two independent parts: a feedback loop for low-frequency jitter tracking and a feedforward path for high-frequency jitter compensation. The feedforward path extracts jitter directly from the transmitted clock without being constrained by feedback loop bandwidth limitations, thereby resolving the contradiction between stability and precision.
Solution Approach 2:
The patent applies preliminary action by pre-compensating for high-frequency jitter using the feedforward path before the data reaches the feedback loop. The jitter is extracted from the transmitted clock in advance and used to pre-adjust the sampling timing, eliminating the need for the feedback loop to track all frequency components.
2Measurement precision
If the feedback loop bandwidth is increased to track more jitter, then the measurement precision of sampling jitter is improved, but the stability is degraded due to amplification of transmitter clock jitter above the loop bandwidth
Solution Approach 1:
The patent divides the jitter compensation task into two frequency domains: the feedback loop handles low-frequency jitter to maintain stability, while the feedforward path handles high-frequency jitter to improve precision. This segmentation allows each path to operate within its optimal bandwidth without causing instability.
Solution Approach 2:
The patent introduces an intermediary feedforward path that acts as a mediator between the transmitted clock and the sampling circuit. This intermediary extracts and compensates for high-frequency jitter independently, allowing the feedback loop to maintain its stable low-frequency tracking without being overwhelmed by high-frequency components.
3Device complexity
If conventional feedback loop is used for jitter correction, then the device complexity is kept simple, but the manufacturing precision of jitter correction is insufficient due to untracked jitter above loop bandwidth
Solution Approach 1:
The patent merges the feedback loop and feedforward path into a unified jitter correction system. The feedforward path uses the transmitted clock directly to extract jitter, while the feedback loop provides additional stabilization. This combination achieves high-precision jitter correction without requiring a completely complex redesign of the entire system.
Solution Approach 2:
The transmitted clock serves multiple functions: it is used by the feedback loop for phase detection and by the feedforward path for jitter extraction. This multi-functionality allows the system to achieve high correction precision without adding separate dedicated jitter sources, thereby limiting the increase in device complexity.
Data Source
AI summary
Technologies for jitter extraction are described. A receiver device includes an analog-to-digital converter (ADC) and a signal processing circuit. The signal processing circuit includes an equalizer block to output current data based on samples from the ADC. A clock-recovery (CR) block includes a timing error detector (TED) or a phase detector to measure a sampling offset. The CR block can use the sampling offset to control sampling of subsequent data by the ADC. A jitter extraction block can use the sampling offset to re-sample the current data to obtain re-sampled data based on the sampling offset to remove jitter from the current data.