Feedforward Level Translator Layout for High-Speed Multi-Phase Oscillators
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multi-phase oscillator circuits face challenges in achieving high frequency operation due to increased capacitance and signal jitter, which affects the accuracy and matching of phase outputs, especially when driving multiple loads and requiring phase-locked loop (PLL) circuits to operate at very high frequencies.
Innovation Solution
The implementation of a multi-phase oscillator circuit design that includes a ring oscillator circuit with reduced capacitance by connecting each output to only one input transistor of a level translator circuit, and the other input transistor to an output of another level translator circuit, thereby minimizing additional capacitance and signal jitter, and using a PLL circuit with a feedback loop to adjust the phase and frequency of the output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional multi-phase oscillator circuits drive multiple level translator circuits directly, then the circuit can provide multiple phase outputs, but the capacitance increases and signal jitter increases, reducing frequency accuracy
Solution Approach 1:
The circuit segments the loading structure by introducing intermediate level translator circuits between the ring oscillator and the final output stage. Each level translator is driven by a single oscillator phase, dividing the total load into multiple smaller, independently driven segments. This reduces the capacitance each oscillator phase must drive, thereby reducing jitter and improving phase matching accuracy while maintaining high operating frequencies.
Solution Approach 2:
The level translator circuits serve as intermediary stages between the ring oscillator and the final multi-phase outputs. These intermediaries buffer the oscillator phases, isolating the high-frequency oscillation core from the capacitive load of driving multiple outputs directly. This intermediary structure minimizes the impact of load capacitance on the oscillator frequency and phase accuracy.
2Device complexity
If the ring oscillator drives multiple level translator circuits directly, then the circuit complexity is reduced, but the capacitance on each oscillator stage increases, limiting maximum operating frequency
Solution Approach 1:
The circuit segments the loading structure by introducing intermediate level translator circuits between the ring oscillator and the final output stage. Each level translator is driven by a single oscillator phase, dividing the total load into multiple smaller, independently driven segments. This reduces the capacitance each oscillator phase must drive, thereby reducing jitter and improving phase matching accuracy while maintaining high operating frequencies.
3Device complexity
If level translator circuits are driven by multiple oscillator phases simultaneously, then the circuit structure is simplified, but signal jitter increases and phase accuracy deteriorates
Solution Approach 1:
Instead of having multiple oscillator phases drive a single level translator (which causes jitter and phase errors), the circuit inverts the driving relationship: each level translator is driven by a single, dedicated oscillator phase. This reverse configuration ensures that each level translator receives a clean, stable clock signal without the jitter and phase inaccuracies that would result from being driven by multiple phases simultaneously.
Data Source
AI summary
This disclosure relates to multi-phase oscillators for electronic systems. An example system includes multiple level translator circuits and a ring oscillator circuit that includes multiple outputs. Each level translator circuit includes a first input transistor, a second input transistor, and an output. The ring oscillator circuit includes multiple outputs, and each output of the ring oscillator has a different phase. An output of the ring oscillator is coupled to only one input transistor of a level translator circuit, and the other input transistor of the level translator circuit is coupled to an output of another level translator circuit.