Feedforward Timing Synchronization in Packet Networks
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Solution Overview
Problem
Existing timing synchronization systems in asynchronous packet networks face stability issues due to feedback loop architectures, which complicate clock synchronization and are not suitable for accurate timing estimation and multiple clock output requirements.
Innovation Solution
A feedforward timing synchronization method using remote and local timestamps to derive an adjustment signal, allowing the digital controlled oscillator to be adjusted without a feedback loop, employing the Least Square algorithm for accurate frequency and phase error estimation, enabling synchronization with a remote reference clock and supporting multiple clock outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If feedback loop architecture is used for clock synchronization, then clock synchronization can be achieved, but system stability deteriorates due to loop stability issues
Solution Approach 1:
The patent inverts the conventional feedback architecture by implementing a feedforward synchronization system. Instead of using receiver timestamps to adjust the transmitter clock (feedback), the system uses transmitter timestamps to predict and adjust the receiver clock proactively (feedforward). This eliminates the feedback loop that causes stability issues while maintaining synchronization capability.
2Reliability
If feedback loop is used for timing synchronization, then timing synchronization can be achieved, but device complexity increases due to loop stability management requirements
Solution Approach 1:
The patent extracts and removes the feedback loop component from the synchronization system. By eliminating the feedback path that requires stability management, the system reduces complexity while maintaining the essential timing synchronization function through feedforward timestamp comparison and clock adjustment.
3Stability of the object's composition
If feedforward configuration is used for clock adjustment, then system stability is improved, but measurement precision may worsen due to unknown network delay distribution
Solution Approach 1:
The patent applies preliminary action by using the transmitter timestamp (known at transmission time) to proactively adjust the receiver clock before the actual timing error occurs. This feedforward approach, combined with Least Square estimation, allows the system to compensate for network delays predictively, maintaining both stability and precision.
Solution Approach 2:
The patent replaces the mechanical feedback loop system with a computational feedforward system using Least Square algorithms. This substitution transforms the physical feedback mechanism into a mathematical estimation and prediction approach, achieving both stability and precision through algorithmic processing of timestamp data.
Data Source
AI summary
To perform timing synchronization in an asynchronous packet network, remote timestamps representative of a transmitter clock at a transmitter are received over a packet network. These are compared with local timestamps representative of the timing of a local oscillator at the receiver to produce an estimate of the offset between the transmitter clock and the local oscillator at the receiver. This estimate is then used to generate update values for a digital controlled oscillator producing the output clock at the receiver. The system operates in a feedforward configuration wherein the local oscillator at the receiver serves as one input to the offset estimator.