FeFET Band-Engineered Interface Layer for Charge Trapping Reduction
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Solution Overview
Problem
Conventional ferroelectric field effect transistors (FeFETs) face challenges in scaling to smaller dimensions due to variability in fabrication processes, leading to charge trapping issues that hinder the development of non-volatile memory for future technology nodes.
Innovation Solution
The implementation of band-engineered interface layers, specifically a metal oxide interfacial layer with a wide bandgap and high-k properties, is introduced to minimize charge trapping and enhance the performance of FeFETs by optimizing the interface between the ferroelectric material and the channel layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional fabrication processes are used for scaling FeFETs to smaller dimensions, then manufacturing cost and compatibility with existing infrastructure are maintained, but charge trapping issues and device variability increase
Solution Approach 1:
A metal oxide interfacial layer is introduced as an intermediary between the ferroelectric layer and the semiconductor channel. This intermediary layer has a wider bandgap than conventional interfaces, which prevents charge trapping while maintaining compatibility with existing bulk silicon substrate fabrication processes. The metal oxide layer acts as a buffer that resolves the contradiction between using conventional processes and avoiding charge trapping.
Solution Approach 2:
The bandgap parameter of the interfacial layer is changed from conventional values to a wider bandgap material (metal oxide). This parameter change prevents charge trapping by creating a larger energy barrier, while the metal oxide material remains compatible with existing fabrication processes, thus resolving the contradiction between reliability and ease of manufacture.
2Productivity
If transistor size is reduced to increase device density, then capacity increases, but fabrication process variability and charge trapping worsen
Solution Approach 1:
The metal oxide interfacial layer serves as a mediator that stabilizes the interface between the ferroelectric layer and channel, reducing variability introduced by scaling. This intermediary structure maintains consistent electrical characteristics even as device dimensions are reduced to increase density.
Solution Approach 2:
The FeFET structure uses a composite material approach with multiple layers including the metal oxide interfacial layer, ferroelectric layer, and semiconductor channel. This composite structure combines materials with complementary properties to achieve both high density and reduced variability, as each layer contributes specific functions that compensate for scaling challenges.
3Reliability
If metal oxide interfacial layer is introduced to reduce charge trapping, then device stability and performance improve, but device complexity increases
Solution Approach 1:
The metal oxide interfacial layer is applied locally at the critical interface between the ferroelectric layer and semiconductor channel, where charge trapping occurs. This localized approach improves device stability at the specific location needed without adding complexity throughout the entire device structure.
Solution Approach 2:
The metal oxide interfacial layer can be formed using existing fabrication processes such as atomic layer deposition (ALD) or chemical vapor deposition (CVD), which are standard industrial techniques. This makes the additional layer cost-effective and manufacturable despite the increased structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved gate control, stability, and performance of thin film transistors, enabling the fabrication of high-performance FeFETs suitable for embedded non-volatile memory and future technology nodes, with reduced charge trapping and increased endurance.
Implementation Method 1
band-engineered interface layers, specifically a metal oxide interfacial layer with a wide bandgap and high-k properties
Implementation Method 2
metal oxide interfacial layer with a wide bandgap and high-k properties
Implementation Method 3
A ferroelectric oxide material is on the metal oxide material
Data Source
AI summary
Ferroelectric field effect transistors (FeFETs) having band-engineered interface layers are described. In an example, an integrated circuit structure includes a semiconductor channel layer above a substrate. A metal oxide material is on the semiconductor channel layer, the metal oxide material having no net dipole. A ferroelectric oxide material is on the metal oxide material. A gate electrode is on the ferroelectric oxide material, the gate electrode having a first side and a second side opposite the first side. A first source/drain region is at the first side of the gate electrode, and a second source/drain region is at the second side of the gate electrode.