3D FeFET Memory Structure With Buffer Layer for Charge Trapping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling down of semiconductor integrated circuits has led to increased complexity in processing and manufacturing, particularly in 3D memory devices, where challenges such as low mobility of poly-silicon channels, interfacial layer breakdown, and charge trapping issues affect the reliability and endurance of ferroelectric field effect transistors (FeFETs).
Innovation Solution
A 3D memory device is proposed with a buffer layer of high dielectric constant between the ferroelectric layer and the channel layer to reduce interfacial charge trapping, enhancing switchable performance and decreasing operation voltage, thereby improving reliability and endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a poly-silicon channel is used in FeFET, then the device structure is simple and manufacturing is easier, but the channel mobility is low which limits device performance
Solution Approach 1:
The patent changes the material parameter of the channel from poly-silicon to a different semiconductor material with superior mobility characteristics, thereby improving channel mobility while maintaining compatibility with existing FeFET manufacturing processes
Solution Approach 2:
The patent employs composite material structures in the channel region, combining multiple materials with complementary properties to achieve both high mobility and ease of manufacture through established fabrication techniques
2Device complexity
If the ferroelectric layer is placed directly adjacent to the channel layer, then the device structure is simplified, but interfacial charge trapping occurs which degrades reliability
Solution Approach 1:
The patent introduces an interfacial layer as a mediator between the ferroelectric layer and channel layer. This intermediary layer prevents direct contact that causes charge trapping, thereby improving reliability while adding minimal structural complexity
Solution Approach 2:
The patent segments the interface between ferroelectric and channel layers by inserting a thin interfacial layer, dividing the direct interface into two separate interfaces that reduce charge trapping effects
3Use of energy by moving object
If the interfacial layer is made thinner to reduce capacitance, then the operation voltage decreases, but the layer becomes more susceptible to breakdown
Solution Approach 1:
The patent uses composite material composition in the interfacial layer, combining materials with different dielectric properties to achieve low capacitance while maintaining high breakdown resistance through the synergistic effects of the composite structure
Solution Approach 2:
The patent applies local quality by varying the composition and thickness of the interfacial layer at different locations to optimize both capacitance and breakdown resistance according to local electrical field conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of a high dielectric constant buffer layer between the ferroelectric and channel layers in 3D memory devices reduces interfacial charge trapping, enhancing switchable performance, decreasing operation voltage, and increasing the operation window, thus improving the reliability and endurance of the devices.
Implementation Method 1
a buffer layer of high dielectric constant between the ferroelectric layer and the channel layer to reduce interfacial charge trapping
Data Source
AI summary
Provided are a memory device and a method of forming the same. The memory device includes a substrate, a layer stack, and a plurality of composite pillar structures. The layer stack is disposed on the substrate. The layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The composite pillar structures respectively penetrate through the layer stack. Each composite pillar structure includes a dielectric pillar; a pair of conductive pillars penetrating through the dielectric pillar and electrically isolated from each other through a portion of the dielectric pillar; a channel layer covering both sides of the dielectric pillar and the pair of conductive pillars; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the channel layer and the ferroelectric layer.