FeFET Gate Stack Buffer Oxide for Interface Film Suppression

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Solution Overview

Problem

The integration of hafnium-based oxides in semiconductor devices faces challenges due to the natural formation of an interface film between the substrate and the gate insulating film, which can lead to charge trapping and deterioration of ferroelectric field effect transistor (FeFET) characteristics, such as reduced endurance and memory window.

Innovation Solution

A semiconductor device structure is developed with a gate insulating film made of hafnium-based oxide, a buffer oxide film, and a buffer film, where the buffer film is used to eliminate or reduce the interface film by applying mechanical stress during an annealing process, enhancing the ferroelectricity and stability of the gate insulating film.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If hafnium-based oxide is used as gate insulating film, then ferroelectricity is maintained in thin films, but interface film formation causes charge trapping and deteriorates FeFET characteristics

Engineering Contradiction:
ImproveFeFET characteristicsVSAvoidinterface film formation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

A buffer oxide film is introduced as an intermediary layer between the hafnium-based oxide gate insulating film and the gate electrode. This buffer oxide film prevents direct contact and interaction between the gate electrode and the gate insulating film, thereby eliminating the formation of harmful interface films while maintaining the ferroelectric properties of the hafnium-based oxide in thin film configuration.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If buffer oxide film is added between gate insulating film and gate electrode, then interface film is reduced and FeFET characteristics are improved, but device structure becomes more complex

Engineering Contradiction:
Improveendurance and memory windowVSAvoidgate structure layers
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The buffer oxide film is designed with specific thickness parameters (greater than 5 nm) to effectively prevent interface film formation while maintaining compatibility with existing semiconductor fabrication processes. By optimizing the thickness parameter, the solution achieves improved FeFET characteristics without requiring fundamental changes to the device architecture or manufacturing complexity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the characteristics of the FeFET by reducing the thickness of the interface film, thereby enhancing the endurance and memory window, and maintaining ferroelectricity even in thin films, contributing to the miniaturization of semiconductor devices.

Implementation Method 1

performing an annealing process

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 2

the buffer film is used to eliminate or reduce the interface film by applying mechanical stress during an annealing process

Methodology Applied
Scientific EffectMechanical stress: Mechanical Force

Data Source

PatentEP4283683A1Semiconductor devices and methods for fabricating the same
Publication Date: 2023.11.29 SAMSUNG ELECTRONICS CO LTD
  • EP4283683A1 patent drawingFigure 1~2
  • EP4283683A1 patent drawingFigure 3~4
  • EP4283683A1 patent drawingFigure 5~6

AI summary

A semiconductor device including a ferroelectric field effect transistor (FeFET) and a method for fabricating the same are provided. The semiconductor device includes a substrate (100), a gate electrode film (140) including a metal element, on the substrate (100), a gate insulating film (120) including a ferroelectric material between the substrate (100) and the gate electrode film (140), and a buffer oxide film (135) including an oxide of a semiconductor material between the gate insulating film (120) and the gate electrode film (140), the buffer oxide film (135) being in contact with the gate insulating film (120).