FeFET Capacitive Read-Out for Low-Power In-Memory Computing
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Solution Overview
Problem
Traditional computing architectures separate processing units and memory components, leading to bottlenecks in system throughput and energy efficiency due to data transfer between these elements, and ferroelectric field effect transistors face challenges with variability, reliability, and scaling issues that limit their practical implementation and performance in in-memory computing.
Innovation Solution
A capacitive read-out mode for ferroelectric field effect transistors that utilizes polarization-dependent capacitance variations to store and retrieve information, enabling non-destructive read operations and reducing power consumption by measuring capacitance between terminals, allowing for charge-domain vector-matrix multiplication in capacitive crossbar arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional resistive crossbar arrays are used for in-memory computing, then vector-matrix multiplication can be performed through current-domain computing, but static power consumption occurs during operation and voltage drops affect computational accuracy
Solution Approach 1:
The patent replaces the resistive (current-domain) computing mechanism with a capacitive (charge-domain) computing mechanism. Instead of using resistance variations to perform computations, the invention uses capacitance variations in ferroelectric field effect transistors to store and process information through charge accumulation and release, eliminating the continuous current flow that causes static power consumption in resistive systems
Solution Approach 2:
The invention changes the fundamental operating parameter from resistance (in resistive crossbars) to capacitance (in ferroelectric FETs). By utilizing the capacitive properties of ferroelectric materials and measuring capacitance changes in response to polarization states, the system performs computing operations without the continuous power consumption inherent in resistive approaches
2Measurement precision
If large current flows are used during read operations in traditional memory systems, then sufficient signal strength is achieved, but power consumption increases and device longevity decreases
Solution Approach 1:
The patent substitutes current-based read operations with capacitance-based read operations. Instead of measuring current flow that requires large signal levels, the invention measures capacitance changes that occur in response to polarization states, enabling detection with minimal current flow and thus reducing power consumption while preserving device longevity
Solution Approach 2:
The invention introduces capacitance measurement as an intermediary mechanism between the stored polarization state and the read signal. The capacitance acts as a mediator that translates the polarization state into a measurable electrical property without requiring large current flows, thereby achieving sufficient signal strength for accurate reading while minimizing power consumption
3Ease of operation
If data is frequently transferred between separate processing and memory units, then computational operations can be performed, but system throughput is reduced and energy efficiency decreases
Solution Approach 1:
The patent merges the memory storage function with the computational processing function by implementing in-memory computing using ferroelectric field effect transistors. The same physical structure that stores data (the ferroelectric FET with its polarization states) also performs computational operations (vector-matrix multiplication through capacitance-based charge-domain computing), eliminating the need for frequent data transfer between separate memory and processing units
Solution Approach 2:
The invention makes the ferroelectric FET structure universal by enabling it to perform both memory storage and computational processing functions. The device can store information through polarization states and simultaneously perform arithmetic operations through capacitance-based charge-domain computing, creating a multi-functional component that improves system throughput by eliminating the memory-wall bottleneck
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances power efficiency and operational stability by eliminating the need for large current flows during read operations, improving device longevity and enabling parallel processing through multilevel storage capabilities and reduced data movement overhead.
Implementation Method 1
measuring capacitance between the gate terminal and the connected source and drain terminals to determine a capacitance state of the ferroelectric field effect transistor. The capacitance state may correspond to either a high capacitance state or a low capacitance state based on polarization of a ferroelectric gate stack
Implementation Method 2
measuring capacitance between the gate terminal and the connected source and drain terminals to determine a capacitance state
Data Source
AI summary
The present disclosure provides a method for operating a ferroelectric field effect transistor (FeFET) as a capacitive memory device. The method comprises connecting a source terminal and a drain terminal of the FeFET together, applying a small-signal voltage to a gate terminal of the FeFET at zero direct-current gate voltage, and measuring capacitance between the gate terminal and the connected source and drain terminals to determine a capacitance state of the FeFET. The capacitance state corresponds to either a high capacitance state or a low capacitance state based on polarization of a ferroelectric gate stack of the FeFET. The disclosure also provides a FeFET device configured for capacitive memory operation comprising a semiconductor channel, a ferroelectric gate stack disposed over the semiconductor channel, a gate terminal connected to the ferroelectric gate stack, a source terminal and a drain terminal connected to the semiconductor channel, and a body terminal. The FeFET device is configured to operate in a capacitive read-out mode where capacitance is measured between the gate terminal and connected source and drain terminals at zero direct-current gate voltage to determine a memory state.