FeFET Dual Passivation Interface for Uniform Ferroelectric Switching
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Solution Overview
Problem
Conventional ferroelectric field effect transistors (FeFETs) face challenges in achieving uniform ferroelectric characteristics due to interfacial excess metal ions and varying oxygen concentrations at the ferroelectric and metal oxide semiconductor interface, leading to instability and non-uniform switching.
Innovation Solution
The implementation of an interfacial dual passivation layer comprising a metal-rich metal oxide layer and a dielectric metal nitride layer, formed through nitridation treatment or deposition processes, to stabilize the interface and reduce metal-metal coordination, thereby enhancing ferroelectric switching and device uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional ferroelectric interface is used without passivation, then device structure is simpler, but ferroelectric characteristics are non-uniform and unstable due to interfacial excess metal ions and varying oxygen concentrations
Solution Approach 1:
The patent introduces an interfacial passivation layer as an intermediary between the ferroelectric layer and the metal oxide semiconductor layer. This passivation layer mediates the interface by reducing metal-metal coordination and stabilizing oxygen concentrations, thereby improving ferroelectric characteristics without directly modifying the bulk materials.
Solution Approach 2:
The patent employs a composite interface structure consisting of multiple materials (ferroelectric material, passivation layer, and metal oxide semiconductor) working together. The passivation layer is specifically engineered with properties that bridge the ferroelectric and semiconductor layers, creating a composite system that achieves both structural stability and enhanced ferroelectric performance.
2Manufacturing precision
If interfacial passivation layer is added to stabilize the interface, then ferroelectric switching uniformity is improved, but manufacturing process complexity increases
Solution Approach 1:
The passivation layer is formed preliminarily at the interface between the ferroelectric and metal oxide semiconductor layers before final device assembly. This preliminary action of creating a stable interface early in the fabrication process prevents subsequent issues with metal ion migration and oxygen variation, ensuring uniform ferroelectric switching characteristics.
3Stability of the object's composition
If metal-rich metal oxide layer and dielectric metal nitride layer are deposited to form dual passivation, then interface stability is enhanced, but deposition process time and complexity increase
Solution Approach 1:
The passivation layer is segmented into two distinct functional layers: a metal-rich metal oxide layer that reduces metal-metal coordination, and a dielectric metal nitride layer that provides additional interface stabilization. This segmentation allows each layer to perform its specific function efficiently, achieving superior interface stability through coordinated action of specialized sub-layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The interfacial dual passivation layer stabilizes the ferroelectric characteristics, reduces variability, and facilitates uniform switching, improving the stability and endurance of ferroelectric memory devices by reducing energy barriers and operational voltage.
Implementation Method 1
The interfacial dual passivation layer may include a metal-rich metal oxide layer and a dielectric metal nitride layer formed over the metal-rich metal oxide layer
Implementation Method 2
The metal-rich metal oxide layer may include a non-stoichiometric and metal-rich oxide
Data Source
AI summary
A semiconductor structure includes, from bottom to top or from top to bottom, a gate electrode, a ferroelectric dielectric layer, a metal-rich metal oxide layer, a dielectric metal nitride layer, and a metal oxide semiconductor layer. A ferroelectric field effect transistor may be provided by forming a source region and a drain region on the metal oxide semiconductor layer. The metal-rich metal oxide layer and the dielectric metal nitride layer homogenize and stabilize the interface between the ferroelectric dielectric layer and the metal oxide semiconductor layer, and reduce excess oxygen atoms at the interface, thereby improving switching characteristics of the ferroelectric field effect transistor.


