FeFET Gate Heating to Lower Write Voltage in Scaled Memory
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Solution Overview
Problem
Ferroelectric field effect transistors (FeFETs) face challenges in scaling down due to the ferroelectric layer's thickness requirements, which affect write voltage and ferroelectric properties, leading to increased complexity and inefficiency in manufacturing.
Innovation Solution
The ferroelectric layer's temperature is elevated prior to or during the write operation using a heater circuit, reducing the potential barrier between polarization states and lowering the write voltage without compromising thickness, thereby improving the ferroelectric properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ferroelectric layer thickness is increased to maintain sufficient polarization, then the ferroelectric properties are improved, but the write voltage increases
Solution Approach 1:
The patent changes the temperature parameter of the ferroelectric layer during write operation. By heating the ferroelectric layer to elevated temperatures (e.g., above Curie temperature or close to it), the coercive field is reduced, which lowers the write voltage requirement while maintaining the necessary polarization for reliable operation. This temporal parameter change resolves the contradiction between maintaining ferroelectric properties and reducing write voltage.
2Power
If the ferroelectric layer thickness is decreased to reduce write voltage, then the power consumption is reduced, but the ferroelectric properties deteriorate
Solution Approach 1:
The patent applies temperature parameter changes to compensate for reduced ferroelectric layer thickness. By dynamically heating the ferroelectric layer during write operations, the system maintains sufficient polarization and ferroelectric properties even with thinner layers, thereby reducing write voltage and power consumption without sacrificing reliability.
3Productivity
If device geometry is scaled down to increase functional density, then the productivity is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent incorporates a heater circuit into the gate structure that is formed along with the transistor during standard fabrication processes. This preliminary integration of the heating functionality eliminates the need for separate heating structures or processes, thereby reducing manufacturing complexity while enabling the temperature-based solutions that allow further scaling and increased functional density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the write voltage and maintains the ferroelectric properties of the FeFET, enhancing the efficiency and scalability of the device by dynamically adjusting the coercive field.
Implementation Method 1
a current is flowed from one of the conductive contacts through the gate electrode to the other conductive contact to increase a temperature of the gate electrode
Implementation Method 2
the ferroelectric layer's temperature is elevated prior to or during the write operation using a heater circuit, reducing the potential barrier between polarization states
Data Source
AI summary
A device and methods of forming the same are described. The device includes a substrate, source/drain regions disposed over the substrate, a ferroelectric layer disposed over the substrate, a gate electrode in contact with the ferroelectric layer, a first conductive contact disposed at a first end of the gate electrode, and a second conductive contact disposed at a second end opposite the first end of the gate electrode. The first and second conductive contacts are configured to allow a current to flow from the first conductive contact through the gate electrode to the second conductive contact.