FeFET Ferroelectric Gate Stack for Low-Voltage Memory Retention
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Solution Overview
Problem
Ferroelectric field effect transistors (FeFETs) face challenges in achieving sufficient memory window at reduced writing voltages due to the thickness of the interfacial layer, which requires high operating voltages and compromises data retention and rewrite withstand capabilities.
Innovation Solution
A method for making semiconductor ferroelectric memory devices with a thinner interfacial layer, utilizing a bismuth layer perovskite ferroelectric film and specific metal and gas annealing conditions to reduce the interfacial layer thickness below 3.4 nm, allowing for ferroelectric film thicknesses between 59 nm and 150 nm, enabling data retention for over 10^5 seconds and rewrite withstand of 10^8 times with a writing voltage of less than 3.3 volts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If annealing is performed in an oxygen atmosphere to crystallize the Bi layer perovskite, then ferroelectricity is achieved and data retention is improved, but the interfacial layer thickness increases to 3.4-5 nm requiring high writing voltages
Solution Approach 1:
The patent changes the gas composition parameter during annealing from pure oxygen to a mixed atmosphere (nitrogen with 0.0002-0.02 volume proportion of oxygen), which modifies the oxidation rate and controls interfacial layer thickness to below 3.4 nm, reducing writing voltage requirements while maintaining data retention
Solution Approach 2:
The patent uses a composite gas atmosphere (nitrogen + oxygen mixture) during annealing instead of pure oxygen, creating a controlled chemical environment that produces the desired interfacial layer thickness without excessive oxidation, thereby reducing writing voltage while preserving ferroelectric properties
2Use of energy by moving object
If the interfacial layer thickness is reduced below 3.4 nm, then writing voltage is reduced, but data retention and rewrite withstand capabilities are compromised
Solution Approach 1:
The patent optimizes multiple parameters simultaneously: gas composition (0.0002-0.02 volume proportion O2 in N2), annealing temperature (700-830°C), and time (10-60 minutes) to achieve the precise interfacial layer thickness range that enables low writing voltage while maintaining adequate data retention and rewrite withstand capabilities
3Manufacturing precision
If conventional annealing conditions are used, then ferroelectric crystallization is achieved, but the FeFET cannot be nanofined due to thick interfacial layer
Solution Approach 1:
The patent modifies annealing parameters (gas composition with 0.0002-0.02 volume proportion O2 in N2, temperature 700-830°C, time 10-60 minutes) to produce a thin interfacial layer below 3.4 nm, enabling ferroelectric film thickness reduction to 59-150 nm and achieving device nanofining while maintaining crystallization quality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in a FeFET with improved data retention and rewrite endurance at reduced voltages, achieving a wider memory window and maintaining excellent electrical characteristics.
Implementation Method 1
annealing is performed in an oxygen atmosphere for a time period of 10 to 60 minutes to crystallize the Bi layer perovskite
Implementation Method 2
annealing is performed in an oxygen atmosphere for a time period of 10 to 60 minutes to crystallize the Bi layer perovskite
Implementation Method 3
a silicon surface is oxidized to form the interfacial layer mainly composed of SiO 2
Implementation Method 4
the gate laminate of electrode conductor / ferroelectric / insulator / semiconductor is comprised of metal Pt, SBT (Sr Bi 2 Ta 2 O 9 ) as a sort of crystal of Bi layered perovskite structure
Data Source
Figure 1~3
Figure 4~5
Figure 6~6(b)
AI summary
Described is a FeFET and a method of its manufacture, the FeFET having a ferroelectric whose film thickness (dr) is in the range: 59 nm < dr < 150, without impairing the data retention property of not less than 105 seconds and the data rewrite withstand property of not less than 108 times, and the FeFET allowing data to be written with a writing voltage whose absolute value is not more than 3.3 volts. The method comprises sequentially forming in the indicated order on a semiconductor substrate an insulator, a bismuth layered perovskite crystalline ferroelectric film and a metal. The stack is annealed for ferroelectric crystallization. Preferably, the film is composed of Ca. Sr, Bi, Ta and oxygen atoms, the metal is Ir or Pt or an alloy of Ir and Pt, or Ru, and the annealing is performed in a mixed gas having oxygen added to nitrogen or a mixed gas having oxygen added to argon.