FeFET Transistor Interface Layer for Charge Trapping Reduction
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Solution Overview
Problem
Existing FeFET-type transistors face challenges in improving certain aspects, particularly in achieving a clean interface between the gate insulator and channel region to reduce charge-trapping asperities and defects, which affect their performance.
Innovation Solution
A method for manufacturing a FeFET-type transistor involves depositing a hafnium oxide gate insulator layer on a semiconductor substrate, followed by a nucleation-promoting layer favoring an orthorhombic crystal structure, and alternating layers of ferroelectric materials, with an interface layer of silicon oxynitride, to enhance crystal structure control and reduce defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a gate insulator layer is deposited directly on the substrate, then the manufacturing process is simpler, but the interface cleanliness is poor and charge-trapping asperities increase
Solution Approach 1:
The gate insulator system is segmented into multiple functional layers: an interface layer (silicon oxynitride) deposited on the substrate, and a ferroelectric layer (hafnium oxide) deposited on the interface layer. This segmentation allows each layer to perform its specific function - the interface layer provides a clean interface with the substrate while the ferroelectric layer provides the desired electrical properties, thereby improving interface cleanliness without excessive complexity.
Solution Approach 2:
An interface layer made of silicon oxynitride is introduced as an intermediary between the substrate and the ferroelectric gate insulator layer. This intermediary layer serves as a buffer that improves the interface cleanliness and reduces charge-trapping asperities at the substrate-insulator interface, while still allowing the ferroelectric layer to function effectively.
2Reliability
If alternating layers of nucleation-promoting materials and ferroelectric materials are deposited, then the orthorhombic crystal structure is enhanced, but the manufacturing process becomes more complex
Solution Approach 1:
A nucleation-promoting layer is deposited on the substrate before depositing the ferroelectric layer. This preliminary action prepares the surface to favor the formation of the desired orthorhombic crystal structure during subsequent ferroelectric layer deposition, thereby enhancing ferroelectric behavior without requiring complex post-processing steps.
Solution Approach 2:
The crystal structure parameters are controlled by introducing nucleation-promoting layers that favor orthorhombic phase formation. By changing the nucleation conditions through these intermediate layers, the ferroelectric layer develops the desired crystal structure with improved reliability, while the layering approach remains compatible with standard deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of transistors with improved interface cleanliness, reduced charge-trapping asperities, and enhanced ferroelectric behavior, allowing for better performance and parallel manufacturing with MOS-type transistors.
Implementation Method 1
depositing an interface layer on the semiconductor substrate, the interface layer including silicon oxynitride; depositing a gate insulator layer on the interface layer
Implementation Method 2
depositing a first layer favoring the nucleation of an orthorhombic crystal structure between the gate insulator layer and the first ferroelectric layer
Data Source
AI summary
A method for manufacturing first and second transistors on a semiconductor substrate includes: depositing an interface layer on the semiconductor substrate; depositing a gate insulator layer on the interface layer; depositing a first ferroelectric layer on the gate insulator layer over a first region for the first transistor; depositing a metal gate layer on the gate insulator layer over a second region for the second transistor and on the first ferroelectric layer over the first region for the first transistor; and patterning the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer to form a first gate stack for the first transistor which includes the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer and a second gate stack for the second transistor which includes the metal gate layer, gate insulator layer and interface layer.