FeFET Memory Cell Lever Capacitor Voltage Distribution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 1T1C ferroelectric field-effect transistor (FeFET) memory cells face challenges in efficient writing and reading operations due to high write voltages and potential read disturbs, primarily because the capacitance ratio between the ferroelectric capacitor and the field-effect transistor capacitance is not optimally controlled, leading to depolarization of the ferroelectric capacitor and ineffective control over the transistor during read operations.
Innovation Solution
Incorporating a lever capacitor structure in addition to the ferroelectric capacitor, allowing for a modified voltage distribution within the memory cell, which reduces write voltages and prevents read disturbs by adjusting the effective capacitance divider during write and read operations, thereby ensuring non-destructive readouts and minimizing depolarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional 1T1C FeFET memory cell structure is used, then the device complexity is low, but the write voltage is high and read disturbs occur
Solution Approach 1:
The memory cell is segmented into two capacitor structures (first capacitor with ferroelectric material and second capacitor without ferroelectric material) connected in series, allowing independent optimization of their respective functions. This segmentation enables the first capacitor to handle write operations while the second capacitor prevents read disturbs, resolving the contradiction between simple structure and reliable operation.
Solution Approach 2:
The second capacitor structure acts as an intermediary element between the first capacitor and the transistor gate. It mediates the voltage distribution during read operations, preventing excessive voltage from reaching the ferroelectric capacitor and causing depolarization. This intermediary structure enables non-destructive read operations while maintaining overall device simplicity.
2Device complexity
If the capacitance ratio between ferroelectric capacitor and transistor capacitance is not optimized, then the device complexity is low, but depolarization occurs during read operations
Solution Approach 1:
The capacitance divider is made dynamic through the second capacitor's ability to be selectively connected or disconnected from the gate node. During read operations, the second capacitor is connected to adjust the capacitance ratio and prevent depolarization. During write operations, it can be disconnected to allow full write voltage application. This dynamic adjustment resolves the contradiction between simple structure and polarization stability.
Solution Approach 2:
The effective capacitance at the gate node is changed based on operational mode. By modifying the capacitance configuration (connecting or disconnecting the second capacitor), the system optimizes the capacitance ratio for either read or write operations. This parameter change enables prevention of depolarization during reads while maintaining write effectiveness, resolving the stability contradiction.
3Productivity
If high write voltages are applied to write operations, then the writing efficiency is high, but the ferroelectric capacitor undergoes depolarization
Solution Approach 1:
The second capacitor is pre-charged to a specific voltage level before write operations. During writing, this pre-charged capacitor helps maintain appropriate voltage levels at the gate node, preventing excessive voltage that would cause depolarization. This preliminary preparation enables high-speed writing while protecting the ferroelectric material, resolving the contradiction between writing efficiency and material stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of a lever capacitor structure enables efficient writing and reading operations with reduced voltage requirements and prevents destructive read disturbances, maintaining the integrity of the ferroelectric material and improving control over the field-effect transistor.
Implementation Method 1
The first capacitor structure may include a ferroelectric material and may be configured to exhibit a first capacitance. The second capacitor structure may be configured to exhibit a second capacitance different from the first capacitance.
Implementation Method 2
allowing for a modified voltage distribution within the memory cell, which reduces write voltages and prevents read disturbs by adjusting the effective capacitance divider during write and read operations
Data Source
AI summary
According to various aspects, a memory cell is provided, the memory cell may include a field-effect transistor; a first control node and a second control node, a first capacitor structure including a first electrode connected to the first control node, a second electrode connected to a gate region of the field-effect transistor, and a remanent-polarizable region disposed between the first electrode and the second electrode of the first capacitor structure; and a second capacitor structure including a first electrode connected to the second control node, a second electrode connected to the gate region of the field-effect transistor. In some aspects, the first capacitor structure may have a first capacitance and the second capacitor structure may have a second capacitance different from the first capacitance.