FeFET Memory Cell With Capacitive Voltage Divider
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Solution Overview
Problem
Current memory technologies face challenges in efficiently storing and retrieving data in a non-volatile manner, particularly in reducing parasitic effects and improving endurance characteristics of memory cells, which limits their application in advanced semiconductor devices.
Innovation Solution
The integration of a ferroelectric field-effect transistor (FeFET) structure with a capacitive memory structure, utilizing a ferroelectric capacitor to store data by controlling the amount of charge, and optimizing the FeCAP layer stack to enhance ferroelectricity and reduce leakage, while using a capacitive voltage divider to reduce the write voltage and depolarization field.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional memory cell structure is used, then the device can store data, but the endurance characteristics are poor and wear out occurs quickly
Solution Approach 1:
The patent changes the physical parameters of the memory cell by integrating a ferroelectric capacitor with optimized layer stack (composition, thickness, crystalline structure) to achieve lower leakage current and reduced depolarization field, thereby improving endurance and reducing wear out while maintaining data storage capability
Solution Approach 2:
The patent employs a composite structure combining ferroelectric material layers with specific dielectric and electrode materials. The ferroelectric capacitor integrates multiple functional layers (ferroelectric layer, dielectric layers, electrode layers) that work together to reduce parasitic effects, minimize leakage, and enhance overall reliability and endurance of the memory cell
2Reliability
If the FeCAP layer stack is optimized to enhance ferroelectricity, then data retention improves, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality optimization by specifically tailoring the ferroelectric layer properties (composition, thickness, crystalline phase) at critical locations within the capacitor stack to maximize ferroelectricity and data retention, while keeping other layers standardized to control manufacturing complexity
Solution Approach 2:
The patent optimizes specific parameters of the FeCAP layer stack including ferroelectric layer thickness, composition ratios, and crystalline structure parameters to enhance ferroelectric properties and data retention, while managing the trade-off with manufacturing process complexity through controlled parameter variations
3Use of energy by moving object
If a capacitive voltage divider is used to reduce write voltage, then energy consumption decreases, but the circuit complexity increases
Solution Approach 1:
The patent introduces a capacitive voltage divider as an intermediary circuit element between the write voltage source and the ferroelectric capacitor. This voltage divider consists of capacitive elements that divide and reduce the write voltage to appropriate levels, thereby reducing energy consumption and preventing over-stress on the memory cell while managing circuit complexity through controlled element addition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient, non-volatile data storage with improved endurance characteristics and reduced wear out of the memory cell, allowing for increased polarization reversals and enhanced data retention.
Implementation Method 1
utilizing a ferroelectric capacitor to store data by controlling the amount of charge
Implementation Method 2
allowing for increased polarization reversals
Implementation Method 3
using a capacitive voltage divider to reduce the write voltage and depolarization field
Implementation Method 4
optimizing the FeCAP layer stack to enhance ferroelectricity and reduce leakage
Data Source
AI summary
According to various aspects, a memory cell comprise: a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal to control the memory cell; a first memory element (FeFET1) and a second memory element (FeFET2), the first memory element comprising a first capacitive memory structure electrically connected to the first terminal and a first field-effect transistor structure coupled to the first capacitive memory structure and electrically connected to the third terminal and the forth terminal; the second memory element comprising a second capacitive memory structure electrically connected to the second terminal and a second field-effect transistor structure coupled to the second capacitive memory structure and electrically connected to the third terminal and the fifth terminal.