FeFET Memory Circuits with Variable Programming Assist Voltages
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Solution Overview
Problem
Threshold voltage programmable field effect transistors (FETs) face challenges in achieving fast and precise programming due to random variations in ferroelectric dielectric materials, requiring repeat programming processes with varying voltage pulses and discrete programming for multi-bit data storage, which reduces write speed and increases complexity.
Innovation Solution
The implementation of variable source-line and bit-line applied programming assist voltages during write operations, with decremental voltages applied during repeat programming processes and specific voltages associated with different multi-bit data values, facilitated by a voltage driver and comparator circuitry to ensure accurate data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If repeat programming processes with varying voltage pulses are used to overcome random variations in ferroelectric dielectric materials, then programming precision is improved, but programming speed deteriorates
Solution Approach 1:
The patent applies dynamics by making the source-line and bit-line voltages adjustable and variable during programming operations. Different voltage combinations are dynamically selected based on the specific programming needs and random variations in the ferroelectric dielectric material, allowing the system to adaptively optimize both precision and speed.
Solution Approach 2:
The patent changes physical parameters by varying the source-line voltage (VSL) and bit-line voltage (VBL) levels during programming. By adjusting these voltage parameters to different combinations (e.g., VSL = 0V and VBL = 2.5V, or VSL = 1.25V and VBL = 1.25V), the system can precisely control the threshold voltage shift while maintaining faster programming speeds.
2Manufacturing precision
If discrete programming approaches are used for multi-bit data storage, then programming precision is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by using a single programming circuit that can handle both single-bit and multi-bit data storage through different voltage combinations. The same source-line and bit-line voltage drivers can program multiple bits concurrently by selecting appropriate voltage levels, eliminating the need for separate discrete programming circuits for each bit.
Solution Approach 2:
The patent merges multiple programming functions into a unified approach where source-line and bit-line voltage combinations serve multiple purposes. The same voltage drivers and control logic are used for both single-bit and multi-bit programming, reducing overall circuit complexity while maintaining programming precision.
3Device complexity
If conventional ground-connected source and drain configurations are used, then device simplicity is maintained, but programming flexibility deteriorates
Solution Approach 1:
The patent transforms the static ground-connected configuration into a dynamic system where source-line and bit-line voltages can be independently controlled and adjusted to different levels. This dynamic voltage control provides programming flexibility while maintaining the basic simplicity of the FET structure.
Data Source
AI summary
Disclosed is a threshold voltage-programmable field effect transistor-based (e.g., a ferro-electric field effect transistor (FeFET)-based) memory circuit employing source-line and/or bit-line-applied variable programming assist voltages. For single-bit data storage in a FeFET, decremental programming assist voltages are selectively applied by a voltage driver to the source-line and/or the bit-line connected to a FeFET during repeat programming processes when previous attempts at programming have failed. For multi-bit data storage in a FeFET, different programming assist voltages are associated with different multi-bit data values and at least one specific programming assist voltage is applied by a voltage driver to the source-line and/or the bit-line connected to a selected FeFET during a programming process to achieve storage of a specific multi-bit data value. Optionally, multiple FeFETs in the same row can be currently programmed with different multi-bit data values. Optionally, different decremental programming assist voltages are applied if/when repeat programming processes are required.