FeFET Array In-Situ Memory Encryption for Secure NVM Access
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Solution Overview
Problem
Non-volatile memories (NVMs) face significant security threats due to their non-volatile property, making them vulnerable to unauthorized data access after power down, and existing encryption solutions like AES incur significant performance and power overhead.
Innovation Solution
A lightweight memory encryption/decryption scheme using in-situ memory operations in FeFET arrays, leveraging XOR operations between data and keys, which does not require additional complex encryption/decryption circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If AES-based encryption is used to secure NVM data, then security against unauthorized access is improved, but performance and power overhead increase significantly
Solution Approach 1:
The patent merges encryption operations with standard memory read/write operations by utilizing the inherent non-volatile properties of NVM cells. The encryption key is directly integrated into the memory cell structure, allowing encryption and decryption to occur automatically during normal memory operations without separate encryption hardware or software layers, thereby eliminating the performance penalty of traditional AES-based solutions
Solution Approach 2:
The memory system performs self-encryption through its intrinsic physical properties. The NVM cell's ability to retain data without power and its natural resistance to reading without proper authentication voltages provide built-in security, eliminating the need for external encryption services and reducing performance overhead
2Reliability
If AES-based encryption is used to secure NVM data, then security against unauthorized access is improved, but power consumption increases
Solution Approach 1:
The patent combines encryption functionality with the memory cell's native read/write operations. By encoding data directly in the NVM cell states and using authentication voltages to control data accessibility, the system eliminates separate encryption/decryption power consumption, achieving security with minimal additional power overhead
Solution Approach 2:
The NVM system provides self-powered security through its physical properties. The non-volatile nature and voltage-dependent readability of the memory cells inherently protect data without requiring continuous power for encryption maintenance, reducing power consumption compared to AES-based solutions that must remain active to maintain security
3Reliability
If traditional encryption hardware is added to NVM, then security is improved, but device complexity increases
Solution Approach 1:
The patent merges encryption logic into the memory cell array structure itself. By using the NVM cells to store both data and key information and utilizing existing word lines and bit lines for authentication operations, the system eliminates separate encryption hardware modules, reducing device complexity while maintaining security
Solution Approach 2:
The memory array structure serves multiple functions simultaneously: data storage, encryption key storage, and authentication verification. The same word lines and bit lines used for normal memory access are also used for encryption operations, eliminating the need for dedicated encryption circuitry and reducing overall device complexity
Data Source
AI summary
Embodiments method for configuring a data structure in a nonvolatile memory (NVM) module that includes at least one memory cell. Each memory cell can have two transistors coupled to each other such that a logic value is stored in a complementary manner. The method can involve encrypting the at least one memory cell by generating a cipher text (CT) by performing an XOR operation on plain text (PT) stored in the at least one memory cell, and performing the XOR operation on a corresponding key. In addition, or in the alternative, the method can involve decrypting cipher text (CT) of the at least one memory cell by applying a read voltage pattern to the two transistors, the read voltage pattern being VR/0 or 0/VR based on a key.