3D FeFET Memory Strings with Oxide Semiconductor Channels
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Solution Overview
Problem
Ferroelectric memory circuits using FeFETs suffer from low endurance, rendering them unsuitable for many memory applications due to their limited ability to withstand programming cycles.
Innovation Solution
A three-dimensional memory structure is developed using thin-film ferroelectric field-effect transistors (FeFETs) organized as NOR memory strings with a ferroelectric gate dielectric layer and an oxide semiconductor channel, allowing for high endurance and long data retention through a 3D array configuration with shared common source and bit lines, and controlled by individual gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If conventional FeFET memory circuits are used, then data retention and non-volatility are improved, but endurance deteriorates due to limited programming cycle tolerance
Solution Approach 1:
The patent changes the material parameter of the channel from conventional semiconductor to oxide semiconductor, which fundamentally alters the device characteristics to achieve both high endurance and data retention. This material parameter change enables the transistor to withstand more programming cycles while maintaining non-volatile memory functionality.
Solution Approach 2:
The invention uses a composite structure combining oxide semiconductor channel with ferroelectric gate dielectric layer. This composite material approach leverages the high endurance of oxide semiconductor and the data retention capability of ferroelectric material to resolve the contradiction between endurance and data retention.
2Quantity of substance
If 3D array configuration is implemented, then memory density is improved, but device complexity increases
Solution Approach 1:
The patent transitions from 2D planar memory arrangement to 3D vertical stacking configuration. Multiple memory layers are stacked in the vertical dimension, significantly increasing memory density while using shared source and bit lines to manage the complexity of interconnections.
Solution Approach 2:
The shared source line and shared bit line structure allows these conductors to serve multiple memory transistors across different layers simultaneously. This multi-functional approach reduces the total number of interconnects needed, managing the complexity associated with 3D configuration.
3Reliability
If oxide semiconductor channel is used, then endurance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs thin-film deposition techniques to create the oxide semiconductor channel layer and ferroelectric gate dielectric layer. The thin-film approach allows for precise control of layer thickness and composition, achieving the required manufacturing precision while enabling the high-endurance oxide semiconductor structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves high-density, low-cost memory arrays with high-speed, randomly accessible memory circuits and low read latency, enabling applications in computing systems as a replacement for conventional RAMs or solid-state drives with improved endurance and data retention.
Implementation Method 1
each thin-film FeFET includes an oxide semiconductor layer and a ferroelectric gate dielectric layer adjacent the oxide semiconductor layer
Data Source
AI summary
A memory structure includes storage transistors organized as horizontal NOR memory strings where the storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent an oxide semiconductor channel region. The ferroelectric storage transistors thus formed are junctionless transistors having no p/n junction in the channel. In some embodiments, the ferroelectric storage transistors in each NOR memory string share a common source line and a common bit line that are formed on a first side of the channel region, away from the ferroelectric gate dielectric layer, and in electrical contact with the oxide semiconductor channel region. The ferroelectric storage transistors in a NOR memory string are controlled by individual control gate electrodes that are formed adjacent the ferroelectric gate dielectric layer on a second side, opposite the first side, of the channel region.