FeFET Memory Circuitry for Refresh Reduction and Disturbance Control
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Solution Overview
Problem
Conventional DRAM technologies rely on capacitors, which require frequent refreshing and are costly to produce, limiting scalability and efficiency, while FeFET-based memory offers advantages like capacitor-less structure, long retention, and better scalability but requires specialized circuits for effective operation.
Innovation Solution
The development of circuitry for FeFET-based memory that includes FeFET-based memory cells, wordlines, bitlines, and sourcelines, with control signals applied to unselected cells to minimize polarization disturbances during program or erase operations, and a refresh circuitry that adjusts thresholds based on the state of reference memory cells to ensure efficient data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DRAM with capacitors is used, then data storage function is achieved, but frequent refreshing is required and production cost is high
Solution Approach 1:
The patent changes the fundamental storage mechanism from capacitor-based charge storage to ferroelectric polarization storage. The ferroelectric material in the FeFET gate exhibits hysteresis in its polarization state, allowing it to maintain stable binary states (0 and 1) without continuous refreshing, thus resolving the contradiction between data retention and refresh frequency
Solution Approach 2:
The patent replaces the passive capacitor-based storage mechanism with an active ferroelectric field-effect transistor that uses electric field-induced polarization. This substitution enables non-volatile storage while maintaining fast switching characteristics, eliminating the need for frequent refreshing operations
2Reliability
If conventional DRAM with capacitors is used, then data storage function is achieved, but production cost is high limiting scalability
Solution Approach 1:
The patent extracts and eliminates the capacitor component from the traditional DRAM cell structure. By using FeFET-based memory cells that rely on ferroelectric polarization rather than charge storage, the design removes the need for separate capacitor structures, simplifying manufacturing and reducing production costs while maintaining data storage functionality
Solution Approach 2:
The FeFET device serves multiple functions: it acts as both the storage element (through ferroelectric polarization) and the access transistor (through field-effect control). This multi-functionality consolidates what would traditionally require separate capacitor and transistor components, reducing manufacturing complexity and cost
3Reliability
If control signals are applied to unselected cells during program/erase operations, then polarization disturbances in unselected cells are minimized, but circuit complexity increases
Solution Approach 1:
The patent applies preliminary protective voltages to unselected cells before and during program/erase operations on selected cells. By pre-establishing appropriate voltage levels on bitlines and sourcelines of unselected cells, the ferroelectric polarization in these cells is protected from unwanted disturbances, ensuring data integrity without requiring complex real-time monitoring circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient operation of FeFET-based memory with reduced refresh frequency, improved data retention, and cost-effective production, addressing the limitations of conventional DRAM technologies by minimizing disturbances to unselected cells and dynamically adjusting refresh thresholds.
Implementation Method 1
FeFET-based data memory cells arranged in an array having rows and columns and capable of being polarized to set memory values of the FeFET-based memory cells to a logic one or a logic zero
Data Source
AI summary
Exemplary embodiments of the present disclosure are directed to circuitry for effective operation of Ferroelectric-gated FET (FeFET) memories. Exemplary embodiment of the present disclosure includes circuits and/or circuit blocks to facilitate memory refresh, error checking and correcting (ECC), reading and sensing memory cells, program and erase operations, and other control and periphery operations for FeFET memory cell arrays.