FeFET Gate-Interposed Layer for Wider Memory Window

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Solution Overview

Problem

Existing ferroelectric field effect transistors face challenges in achieving a sufficient memory window, which is crucial for improving operational reliability in logic devices and memory devices.

Innovation Solution

Incorporating a gate-interposed layer with a paraelectric material between the ferroelectric layer and the gate electrode, featuring a first interposed region adjacent to the ferroelectric layer and a second interposed region adjacent to the gate electrode, where the first interposed region includes a mixture of the first and second elements with an average ratio of the first element greater than in the ferroelectric layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional ferroelectric field effect transistor structure is used, then the device can operate with ferroelectric threshold voltage variation, but the memory window is insufficient for improved operational reliability

Engineering Contradiction:

Improveoperational reliabilityVSAvoidmemory window

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

A gate-interposed layer comprising a paraelectric material is introduced between the gate electrode and the ferroelectric layer. This intermediary layer reduces the overall capacitance between the gate electrode and the ferroelectric layer, thereby increasing the memory window and improving operational reliability without altering the fundamental ferroelectric switching mechanism.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate stack is configured as a composite structure combining the gate electrode, the gate-interposed layer with paraelectric material, and the ferroelectric layer. This composite configuration allows the system to leverage both the paraelectric properties of the interposed layer (for capacitance reduction) and the ferroelectric properties of the ferroelectric layer (for threshold voltage switching), achieving enhanced memory window and reliability.

Inventive Principle:

Principle #40Composite materials

2Quantity of substance

If the capacitance between gate electrode and ferroelectric layer is high, then stronger coupling is achieved, but the memory window decreases reducing operational reliability

Engineering Contradiction:

Improvememory windowVSAvoidcapacitance

Core Design Contradiction:

Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The gate-interposed layer acts as a mediator that reduces the capacitive coupling between the gate electrode and the ferroelectric layer. By lowering the overall capacitance, the memory window is increased, allowing for better distinction between threshold voltage states and improved operational reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The dielectric constant of the gate-interposed layer is specifically selected to be 8 or less, which is significantly lower than conventional gate dielectrics. This parameter change in dielectric constant directly reduces the overall capacitance of the gate stack, thereby increasing the memory window and improving device reliability.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the memory window by reducing the overall capacitance between the gate electrode and the ferroelectric layer, thereby improving the operational reliability of the ferroelectric field effect transistor.

Implementation Method 1

a gate-interposed layer between the ferroelectric layer and the gate electrode and including a paraelectric material including an oxide of a second element different from the first element

Methodology Applied

Scientific EffectParaelectric effect: Dielectric Permittivity

Data Source

PatentUS20250056844A1Ferroelectric field effect transistor, memory device, and neural network apparatus including gate-interposed layer

Publication Date: 2025.02.13 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided is a ferroelectric field effect transistor including a source region, a drain region, a channel provided between the source region and the drain region, a ferroelectric layer provided on the channel and including a ferroelectric material including an oxide of a first element, a gate-interposed layer provided on the ferroelectric layer and including a paraelectric material including an oxide of a second element different from the first element, and a gate electrode provided on the gate-interposed layer, wherein the gate-interposed layer includes a first interposed layer adjacent to the ferroelectric layer, and a second interposed layer adjacent to the gate electrode, the first interposed layer includes a mixture of the first element and the second element, and a ratio of the first element in the first interposed layer may be greater than a ratio of the first element in the ferroelectric layer.