FeFET Multiply-Accumulate Circuit for Low-Power Precision
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Solution Overview
Problem
Existing in-memory computing technologies face challenges in achieving efficient and precise multiply and accumulate operations, particularly in artificial intelligence applications, due to high power consumption, heat generation, and precision limitations in conventional memristors and FeFET arrays.
Innovation Solution
A multiply operation circuit and multiply and accumulate circuit utilizing a combination of field-effect transistors and programmable switches, specifically ferroelectric field-effect transistors (FeFETs), which allow for low-power analog operations with precise threshold control, reducing voltage drops and enabling large arrays with accurate current flows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional memristors and FeFET arrays are used for in-memory computing, then multiply and accumulate operations can be performed, but power consumption increases and heat generation occurs
Solution Approach 1:
The patent changes the operating parameters by using subthreshold region operation of field-effect transistors to achieve ultra-low power consumption. By operating FETs in the subthreshold region rather than full saturation, the circuit achieves multiply-accumulate operations with minimal power dissipation while maintaining computational functionality.
Solution Approach 2:
The patent replaces conventional resistive switching mechanisms (memristors) with field-effect transistor-based switching. This substitution enables more efficient control of current flow through voltage-gated FETs rather than resistance-gated memristors, reducing power consumption and heat generation during MAC operations.
2Measurement precision
If conventional memristors are used for multiply and accumulate operations, then computing can be performed in-memory, but precision is limited
Solution Approach 1:
The patent substitutes memristor-based resistive switching with field-effect transistor-based switching. FETs provide superior voltage control and threshold precision compared to memristors, enabling more accurate representation of weight values and improved precision in analog neural network computations.
Solution Approach 2:
The patent utilizes the subthreshold slope parameter of FETs to achieve precise control of current flow. By operating in the subthreshold region, the FET's exponential current-voltage relationship provides fine-grained control over conductance values, enabling high-precision analog computing without the precision limitations of memristor-based approaches.
3Use of energy by moving object
If FeFET arrays are used for in-memory computing, then operations can be performed with lower power, but voltage drops increase
Solution Approach 1:
The patent segments the FeFET array into multiple subarrays with shared word lines and bit lines. This segmentation allows selective activation of specific subarrays during computation, reducing the total current flow through any single row and thereby minimizing voltage drops while maintaining power efficiency across the large-scale array.
Solution Approach 2:
The patent employs partial action by activating only the necessary portion of the FeFET array for each compute operation. Through sequential activation of subarrays and reuse of hardware resources, the system achieves low voltage drops by avoiding simultaneous full-array operation, while still providing sufficient computational capacity.
4Productivity
If large arrays of operation cells are implemented, then computational capacity increases, but manufacturing complexity increases
Solution Approach 1:
The patent implements universality through shared word lines and bit lines that serve multiple FET rows and columns respectively. This multi-functional wiring architecture allows a single word line to control multiple FETs across different rows, and a single bit line to serve multiple FETs across columns, dramatically reducing the total wiring complexity while enabling large array implementations.
Solution Approach 2:
The patent merges multiple FETs into functional groups that share common control lines and signal lines. By combining multiple operation cells into modular subarrays with shared infrastructure, the patent reduces individual cell complexity and simplifies manufacturing while scaling up overall computational capacity through the aggregation of these modular units.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables power-efficient, precise multiply and accumulate operations with reduced voltage drops, allowing for large arrays and efficient processing of artificial intelligence workloads with improved endurance and accuracy.
Implementation Method 1
a field-effect transistor having a first source/drain terminal, a second source/drain terminal, and a control terminal... configured to control a current flow between the first control line and the second control line as a function of both a first control voltage provided at the control terminal of the field-effect transistor
Implementation Method 2
a switch having at least a first terminal and a second terminal... configured to control a current flow between the first control line and the second control line as a function of... a switch state in which the switch is residing in
Data Source
AI summary
Various aspects relate to a multiply and accumulate circuit, the multiply and accumulate circuit including: a plurality of multiply operation cells configured in a matrix arrangement. A respective multiply operation cell of the multiply operation cells includes: a field-effect transistor and a programmable switch in a series connection, wherein the field-effect transistor and the programmable switch are configured to control a current flow through the respective multiply operation cell to realize a multiplication operation. The multiply operation cells of a set of the plurality of multiply operation cells share a corresponding control line to realize an accumulation operation in addition to the multiply operations carried out by the set of multiply operation cells.