FeFET Polarization Enhancement Structure for Larger Memory Windows
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Solution Overview
Problem
Ferroelectric random-access memory (FeRAM) devices with oxide semiconductor channel regions have a limited memory window due to the inability to accumulate both electrons and holes, reducing their performance compared to semiconductor-based channel regions.
Innovation Solution
Incorporating a polarization enhancement structure with a different semiconductor type between the source and drain regions on an oxide semiconductor channel, allowing charge carriers to reinforce polarizations in the ferroelectric material, thereby increasing the memory window by differentiating threshold voltages for data states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an oxide semiconductor channel region is used in FeFET devices, then the device structure is simplified and CMOS compatibility is improved, but the memory window is limited due to inability to accumulate both electrons and holes
Solution Approach 1:
The channel region is segmented into two distinct parts: an oxide semiconductor channel and a polarization enhancement structure with opposite semiconductor type. This segmentation allows each part to perform specialized functions - the oxide semiconductor provides CMOS compatibility while the polarization enhancement structure accumulates opposite charge carriers to enlarge the memory window
Solution Approach 2:
Different regions of the channel have different semiconductor types optimized for specific functions. The oxide semiconductor region provides CMOS compatibility, while the polarization enhancement structure with opposite doping type is strategically placed to accumulate charge carriers that reinforce ferroelectric polarization, creating local quality variations that solve the memory window limitation
2Reliability
If a semiconductor-based channel region is used instead of oxide semiconductor, then the memory window is enlarged through charge carrier accumulation, but the device complexity and fabrication difficulty increase
Solution Approach 1:
Rather than using a completely different semiconductor material throughout the channel, the structure segments the channel into an oxide semiconductor part and a polarization enhancement part. This allows retention of CMOS-compatible oxide semiconductor fabrication while adding a relatively simple doped region to achieve the memory window enhancement
Solution Approach 2:
The invention changes the semiconductor type parameter (doping polarity) in the polarization enhancement structure relative to the oxide semiconductor channel. This parameter change enables the structure to accumulate opposite charge carriers that reinforce polarization, achieving large memory window without requiring entirely different materials or complex fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the memory window of FeFET devices, improving their performance by allowing charge carriers in the polarization enhancement structure to reinforce polarizations, leading to increased threshold voltage differences and improved data state differentiation.
Implementation Method 1
a first type of charge carriers accumulate within the oxide semiconductor and enhance and/or reinforce the first polarization. When the electric field causes the ferroelectric material to have a second polarization with a second direction, a second type of charge carriers accumulate within the polarization enhancement structure and enhance and/or reinforce the second polarization
Implementation Method 2
During operation, the gate structure is configured to generate an electric field that polarizes the ferroelectric material
Data Source
AI summary
The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. The FeFET device includes a ferroelectric structure having a first side and a second side. A gate structure is disposed along the first side of the ferroelectric structure, and an oxide semiconductor is disposed along the second side of the ferroelectric structure. The oxide semiconductor has a first semiconductor type. A source region and a drain region are disposed on the oxide semiconductor. The gate structure is laterally between the source region and the drain region. A polarization enhancement structure is arranged on the oxide semiconductor between the source region and the drain region. The polarization enhancement structure includes a semiconductor material or an oxide semiconductor material having a second semiconductor type that is different than the first semiconductor type.