3D FeFET Memory Structure for Read Window and Density Balance
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, the integration density of electronic components increases, but this leads to challenges in maintaining reliable memory storage and read/write operations due to the limitations of existing memory technologies, particularly in achieving high-density 3D memory arrays with efficient ferroelectric materials.
Innovation Solution
The development of a 3D memory array using ferroelectric field effect transistors (FeFETs) with vertically stacked memory cells, incorporating a ferroelectric material as a gate dielectric and an oxide semiconductor channel region, and employing a staircase configuration of conductive lines and pillars to enhance memory density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but reliability of memory storage and read/write operations deteriorates
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional vertically stacked FeFET memory cells. By stacking multiple memory cells vertically along the z-axis, the integration density increases dramatically while each cell maintains adequate lateral dimensions for reliable operation. The staircase configuration of conductive lines and pillars extends into the third dimension, enabling high-density integration without compromising the functional reliability of individual memory cells.
Solution Approach 2:
The patent employs composite material structures including ferroelectric material layers (for gate dielectric), oxide semiconductor channel regions, and multi-layer conductive pillars. These composite structures enable simultaneous achievement of high integration density and reliable memory operation by combining materials with complementary properties - the ferroelectric layer provides non-volatile storage capability while the oxide semiconductor ensures stable channel performance at scaled dimensions.
2Reliability
If ferroelectric material properties are controlled precisely, then read window and error rate improve, but manufacturing complexity increases
Solution Approach 1:
The patent employs systematic parameter control during fabrication, including precise thickness control of ferroelectric layers (e.g., 5-20 nm ranges), controlled orthorhombic phase proportion through deposition conditions, and optimized annealing temperatures. These parameter controls enable precise tuning of ferroelectric properties to achieve large read windows and low error rates. The methodology balances manufacturing complexity by using controllable parameters that can be adjusted through standard deposition and annealing process optimization.
Solution Approach 2:
The patent implements preliminary surface treatment and seed layer formation before depositing ferroelectric materials. These preliminary actions prepare the substrate surface to promote desired crystalline phases and improve ferroelectric property uniformity, thereby achieving reliable read window characteristics while managing manufacturing complexity through standardized preparatory processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves memory density and performance by allowing precise control of ferroelectric material properties, such as orthorhombic phase proportion, leading to enhanced read windows and reduced error rates in digital value storage and retrieval.
Implementation Method 1
a ferroelectric material as a gate dielectric
Data Source
AI summary
Provided is a ferroelectric memory device having a dielectric layer vertically interleaved between a first conductive line and a second conductive line. A first ferroelectric portion is arranged along a sidewall of the first conductive line and a second ferroelectric portion is arranged along a sidewall of the second conductive line. A channel layer is arranged along sides of the dielectric layer, the first conductive line, and the second conductive line. A topmost surface of the first ferroelectric portion is vertically separated from a bottommost surface of the second ferroelectric portion by the channel layer.