FeFET Fabrication Using Sacrificial Stressor Layer for Phase Transition
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Solution Overview
Problem
The challenge in fabricating ferroelectric field-effect transistors (FeFETs) lies in controlling the phase transition of ferroelectric layers while minimizing adverse effects on two-dimensional (2D) material channel layers, which are sensitive to thermal budgets and stress during the fabrication process.
Innovation Solution
A method involving the formation of a layer stack with a ferroelectric layer and a sacrificial stressor layer, where the sacrificial stressor layer undergoes heat treatment to induce a phase transition in the ferroelectric layer, followed by replacement with a 2D material channel layer, thereby controlling ferroelectric properties without exposing the 2D material to high thermal conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If heat treatment is applied to induce phase transition in the ferroelectric layer, then the ferroelectric properties are improved, but the 2D material channel layer is damaged due to thermal sensitivity
Solution Approach 1:
The patent applies preliminary action by forming the sacrificial stressor layer before the 2D material channel layer. This allows the heat treatment to be performed on the ferroelectric layer while the sacrificial layer is present, inducing the desired phase transition. After the heat treatment, the sacrificial layer is removed and replaced with the 2D material channel layer, ensuring the 2D material is never exposed to high temperatures that would cause thermal damage.
Solution Approach 2:
The sacrificial stressor layer acts as an intermediary that enables the heat treatment process. It provides the necessary stress to induce phase transition in the ferroelectric layer during heat treatment, and its temporary presence allows the 2D material to be introduced after the thermal process is complete, thus mediating between the conflicting requirements of heat treatment and 2D material protection.
2Reliability
If sacrificial stressor layer is used to control phase transition, then ferroelectric layer properties are enhanced, but device fabrication complexity increases
Solution Approach 1:
The patent applies parameter changes by utilizing the stressor layer to modify the stress parameter in the ferroelectric layer during heat treatment. This stress parameter change induces the desired phase transition. The sacrificial nature of the stressor layer allows it to be removed after serving its purpose, and the 2D material channel layer is then formed in its place, maintaining device functionality while achieving phase transition control.
3Ease of manufacture
If 2D material channel layer is formed before heat treatment, then fabrication sequence is simplified, but the 2D material is exposed to detrimental thermal budget
Solution Approach 1:
The patent reverses the conventional sequence by applying preliminary action with the sacrificial stressor layer. Instead of forming the 2D material channel layer first and then performing heat treatment, the sacrificial stressor layer is formed first, enabling the heat treatment to occur without exposing the 2D material to high temperatures. The 2D material is then introduced after the thermal process, simplifying the overall fabrication while protecting the sensitive material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the ferroelectric properties of the ferroelectric layer while protecting the 2D material channel layer from thermal stress, allowing for improved device performance and control over ferroelectricity without being limited by the 2D material's thermal budget.
Implementation Method 1
subjecting the layer stack to a heat treatment to cause a phase transition in the ferroelectric layer
Implementation Method 2
The sacrificial stressor layer may contribute to the phase transition by inducing stress in the ferroelectric layer
Implementation Method 3
The heat treatment may improve device performance by annealing the ferroelectric layer. The annealing process may increase or induce ferroelectricity exhibited by the ferroelectric layer
Data Source
AI summary
The disclosed technology generally relates to methods of fabricating a semiconductor device, and more particularly to methods of fabricating a ferroelectric field-effect transistor (FeFET). According to one aspect, a method of fabricating a FeFET includes forming a layer stack on a gate structure, wherein forming the layer stack comprises a ferroelectric layer followed by forming a sacrificial stressor layer. The method additionally includes heat-treating the layer stack to cause a phase transition in the ferroelectric layer. The method additionally includes, subsequent to the heat treatment, replacing the sacrificial stressor layer with a two-dimensional (2D) material channel layer. The method further includes forming a source contact and a drain contact contacting the 2D material channel layer.