FeFET Carrier Barrier Layer for Off-State Power Reduction
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Solution Overview
Problem
Ferroelectric field-effect transistors (FeFETs) based on thin film transistors (TFTs) face challenges with negative threshold and turn-off voltages, leading to reduced power efficiency due to dependence on constant negative voltage to maintain the off state, which also results in mobility and on-current degradation.
Innovation Solution
Incorporating a carrier barrier layer between the source/drain electrodes and the semiconductor structure in FeFETs to tune the threshold voltage, allowing the transistor to maintain the off state with little to no voltage, achieved by using a carrier barrier layer that forms a Schottky barrier and increases the threshold voltage, thereby reducing power consumption without affecting mobility or on-current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional FeFET structure is used, then the device has a simple structure compatible with CMOS fabrication, but the threshold voltage is negative requiring constant negative voltage to maintain off state, leading to reduced power efficiency
Solution Approach 1:
An intermediate layer is introduced between the source/drain electrodes and the semiconductor structure. This intermediate layer acts as a mediator that forms a Schottky barrier, which raises the threshold voltage to positive values. The Schottky barrier prevents carrier injection into the channel when the transistor is off, eliminating the need for constant negative voltage bias and thereby reducing power consumption while maintaining CMOS compatibility
Solution Approach 2:
The threshold voltage parameter is changed from negative to positive by modifying the interface properties between the source/drain electrodes and semiconductor structure. This is achieved by introducing an intermediate layer with specific material properties that create a Schottky barrier, fundamentally changing the electrical characteristics and power consumption behavior of the device
2Use of energy by moving object
If the threshold voltage is increased to improve power efficiency, then power consumption is reduced, but mobility and on-current may be degraded
Solution Approach 1:
The intermediate layer is positioned locally only at the source/drain electrode interfaces where it is needed to form the Schottky barrier. The layer has specific local properties (thickness, material composition) that are optimized to provide the desired barrier height while minimizing impact on the overall device performance. This localized approach allows threshold voltage adjustment without compromising mobility in the channel region
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces power consumption by allowing the FeFET to maintain the off state at reduced or zero voltage, while maintaining high mobility and on-current levels, and decreasing leakage current.
Implementation Method 1
the carrier barrier layer forms a Schottky barrier and increases the threshold voltage
Data Source
AI summary
The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tuning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure.