FeFET Source Extension Asymmetry for Full Ferroelectric Erase
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Solution Overview
Problem
Ferroelectric field effect transistor (FeFET) based memory devices, particularly those using oxide semiconductors, face challenges in achieving uniform electric fields across the ferroelectric layer due to insufficient hole carriers, leading to lower erase efficiency during polarization switching.
Innovation Solution
The implementation of size-asymmetric source and drain extensions in the memory device enhances hole carrier induction in the metal oxide semiconductor layer, increasing the coupling electric field in the ferroelectric dielectric layer, enabling full polarization switching and improved erase efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If oxide semiconductor is used as channel material in FeFET, then device size and power consumption are improved, but erase efficiency deteriorates due to insufficient hole carriers
Solution Approach 1:
The patent implements size-asymmetric source and drain extensions where the source extension has a larger lateral dimension than the drain extension. This asymmetric configuration provides additional hole carriers from the source extension to the oxide semiconductor channel, enabling sufficient hole carriers for full polarization switching in the ferroelectric layer while maintaining the low power consumption benefits of oxide semiconductor FeFET devices.
2Volume of moving object
If oxide semiconductor is used as channel material, then device size is reduced, but uniform electric field across ferroelectric layer cannot be achieved
Solution Approach 1:
The asymmetric source extension structure compensates for the insufficient hole carriers in oxide semiconductor, enabling the generation of uniform electric field across the ferroelectric layer during erase operations while maintaining the small device size characteristic of oxide semiconductor FeFETs.
3Ease of operation
If negative voltage is applied to gate electrode with insufficient hole carriers, then device operation is maintained, but polarization switching in ferroelectric layer is incomplete
Solution Approach 1:
The source extension acts as an intermediary that provides additional hole carriers to the oxide semiconductor channel. This intermediary structure enables complete polarization switching in the ferroelectric layer during erase operations by supplying the necessary hole carriers that are insufficient in the oxide semiconductor alone, while maintaining normal device operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for enhanced coupling electric fields, resulting in a wider memory window and increased erase efficiency during program and erase operations.
Implementation Method 1
a ferroelectric dielectric layer disposed over the gate electrode
Implementation Method 2
a metal oxide semiconductor layer disposed over the ferroelectric dielectric layer
Data Source
AI summary
Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a gate electrode disposed in an insulating material layer, a ferroelectric dielectric layer disposed over the gate electrode, a metal oxide semiconductor layer disposed over the ferroelectric dielectric layer, a source feature disposed over the metal oxide semiconductor layer, wherein the source feature has a first dimension, and a source extension. The source extension includes a first portion disposed over the source feature, wherein the first portion has a second dimension that is greater than the first dimension. The source extension also includes a second portion extending downwardly from the first portion to an elevation that is lower than a top surface of the source feature.