FeFET Ferroelectric Layer Structure for Wake-Up and Leakage Control
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Solution Overview
Problem
Ferroelectric random-access memory (FeRAM) devices with high Zr dopant concentrations suffer from performance instability due to the wake-up effect and current leakage, which degrades endurance and stability, especially in devices with anti-ferroelectric dominant lattice structures.
Innovation Solution
An integrated chip with a ferroelectric field-effect transistor (FeFET) device featuring a ferroelectric layer with an orthorhombic crystalline structure and an anti-ferroelectric layer with a tetragonal crystalline structure, separated by an interlayer that promotes large grain growth and suppresses current leakage, thereby reducing Zr doping levels and enhancing stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high Zr dopant concentrations are used to achieve anti-ferroelectric dominant lattice structure, then memory storage density is improved, but performance stability deteriorates due to wake-up effect and current leakage
Solution Approach 1:
The ferroelectric layer is segmented into multiple thinner sub-layers (e.g., three 5nm layers instead of one 15nm layer) with alternating Zr dopant concentrations. This segmentation reduces the wake-up effect and current leakage while maintaining the anti-ferroelectric dominant lattice structure and memory storage density.
Solution Approach 2:
Different regions of the ferroelectric layer have different Zr dopant concentrations (e.g., 60-80% in first sub-layer, 20-40% in second sub-layer, 60-80% in third sub-layer). This local variation in composition allows the structure to achieve anti-ferroelectric dominance for high storage density while reducing overall current leakage and wake-up effect through lower average Zr concentration.
2Strength
If high Zr dopant concentrations are used to form anti-ferroelectric lattice structure, then ferroelectric properties are enhanced, but current leakage increases which degrades endurance
Solution Approach 1:
The Zr dopant concentration parameter is varied across different sub-layers rather than being uniform. By using alternating high and low Zr concentration regions, the structure maintains strong ferroelectric properties in high-Zr regions while low-Zr regions reduce current leakage, achieving a balance between ferroelectric strength and leakage reduction.
3Quantity of substance
If high Zr dopant concentrations are used to achieve anti-ferroelectric structure, then memory density is improved, but wake-up effect increases which reduces stability
Solution Approach 1:
The ferroelectric layer is divided into multiple thin sub-layers with alternating Zr concentrations. This segmentation reduces the cumulative wake-up effect that occurs in thick high-Zr layers while maintaining the anti-ferroelectric dominant structure necessary for high memory density.
Solution Approach 2:
Alternating regions of high and low Zr concentration create local variations in ferroelectric properties. The low-Zr regions act as buffers that reduce the wake-up effect propagation through the layer, while high-Zr regions maintain the anti-ferroelectric structure for high memory density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the endurance and stability of FeFET devices by reducing the wake-up effect and current leakage, allowing for denser memory storage without compromising performance, while maintaining even Zr distribution and reducing the need for high Zr doping.
Implementation Method 1
an interlayer that promotes large grain growth and suppresses current leakage
Implementation Method 2
a ferroelectric layer with an orthorhombic crystalline structure and an anti-ferroelectric layer with a tetragonal crystalline structure
Data Source
AI summary
The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. The FeFET device includes a ferroelectric structure having a first side and a second side. A gate structure is disposed along the first side of the ferroelectric structure, and an oxide semiconductor is disposed along the second side of the ferroelectric structure. The oxide semiconductor has a first semiconductor type. A source region and a drain region are disposed on the oxide semiconductor. The gate structure is laterally between the source region and the drain region. A polarization enhancement structure is arranged on the oxide semiconductor between the source region and the drain region. The polarization enhancement structure includes a semiconductor material or an oxide semiconductor material having a second semiconductor type that is different than the first semiconductor type.