Feistel Cipher Hardware Accelerator for 3DES Speed and Power
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Solution Overview
Problem
Existing hardware accelerators for cryptography, such as those implementing the Data Encryption Standard (DES) and triple DES (3DES), are slow and power-intensive due to the number of operations required for encryption, especially when running multiple invocations of the DES algorithm.
Innovation Solution
A hardware accelerator design that includes memory areas for bit strings, a calculation block for non-linear mapping, and a controller for managing data flow, allowing for internal data handling and optimized execution of Feistel ciphers, reducing the need for external data handling and minimizing processing steps by retaining data in memory for subsequent invocations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple invocations of the DES algorithm are performed to achieve 3DES encryption, then security is greatly enhanced with 168 independent key bits, but the encryption process becomes relatively slow and requires a relatively large amount of power due to the number of operations required
Solution Approach 1:
The 64-bit plaintext block is divided into two 32-bit sub-blocks (first and second bit strings), which are processed independently through the Feistel network. This segmentation allows parallel processing of different parts of the data, improving throughput while maintaining the required multiple encryption passes for security.
Solution Approach 2:
The hardware accelerator implements a Feistel network structure where the encryption process is nested within itself across multiple rounds. Each round processes the data through substitution boxes (S-boxes) and permutation boxes (P-boxes) that are nested within the overall Feistel structure, allowing efficient implementation of multiple DES invocations needed for 3DES while reducing redundant operations.
2Reliability
If multiple invocations of the DES algorithm are performed to achieve 3DES encryption, then security is greatly enhanced with 168 independent key bits, but the encryption process requires a relatively large amount of power due to the number of operations required
Solution Approach 1:
The hardware accelerator pre-computes and stores substitution tables (S-boxes) and permutation tables (P-boxes) in dedicated memory structures before encryption begins. This preliminary preparation eliminates the need for complex real-time calculations during each encryption round, significantly reducing power consumption while maintaining the security requirements of multiple DES invocations.
Solution Approach 2:
The patent replaces complex mechanical computation operations with pre-computed lookup tables stored in memory. Instead of performing intricate mathematical transformations during each encryption round, the system uses memory-based substitution and permutation operations, which consume significantly less power while achieving the same cryptographic security.
3Ease of operation
If traditional encryption hardware is used, then encryption can be performed, but the execution time of the algorithm is increased due to external data handling operations
Solution Approach 1:
The hardware accelerator merges the data handling operations with the encryption processing by implementing internal data paths that allow sub-blocks to be passed directly between memory areas and processing units without external intervention. This integration eliminates the time-consuming external data handling operations while maintaining ease of operation through a unified interface.
Solution Approach 2:
The controller unit is designed to handle multiple functions including data loading, round key management, substitution operations, permutation operations, and result output within a single integrated structure. This multi-functionality eliminates the need for separate external data handling operations, reducing execution time while maintaining operational simplicity.
Data Source
AI summary
A hardware accelerator is arranged to perform cipher operations and comprises a first memory area arranged to store a first bit string and a second memory area arranged to store a second bit string. A calculation block is arranged to receive a round key and to perform a function on the first bit string. The function comprises combining the first bit string with the round key to produce a combined bit string and performing a non-linear mapping from the combined bit string to a mapped bit string. An addition block is arranged to add the mapped bit string to the second bit string to produce a resultant bit string. A controller is arranged to receive a control signal and, depending on the state of the control signal, provides the first bit string and the resultant bit string to the appropriate memory area.