FEM Wafer Exposure Condition Visualization
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Solution Overview
Problem
In semiconductor device manufacturing, process variations over time lead to drifts in exposure conditions, making it difficult to maintain accurate resist pattern dimensions, as sensors drift and exposure sensitivities change, resulting in suboptimal exposure conditions.
Innovation Solution
A system that calculates and displays feature quantities of the sectional shape of resist patterns on a Focus & Exposure Matrix (FEM) wafer using a scanning electron microscope, allowing for a visual judgment of normal or abnormal exposure conditions by representing deviations in color on a chip table, facilitating easy identification of optimal exposure settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dimension measurement of resist pattern is performed using length measuring SEM to verify process variation, then measurement precision is improved, but it is difficult to visually identify which chip has abnormal exposure condition
Solution Approach 1:
The patent creates a chip table that is a visual copy/map of the FEM wafer chip arrangement. Instead of directly analyzing raw measurement data, the system generates a simplified visual representation where each chip position is represented in the chip table, allowing operators to visually identify abnormal chips without complex measurement analysis.
Solution Approach 2:
The patent applies color coding to represent exposure condition status in the chip table. Chips with normal exposure conditions are displayed in one color state, while chips with abnormal conditions are displayed in different color states, enabling immediate visual identification of problematic chips without detailed measurement analysis.
2Manufacturing precision
If feature quantity calculation is performed for each chip region, then manufacturing precision monitoring is improved, but device complexity increases
Solution Approach 1:
The patent divides the FEM wafer into individual chip regions and processes each chip's resist pattern separately. By segmenting the analysis into discrete chip-level feature quantity calculations, the system can monitor exposure conditions for each chip independently while organizing results in a structured chip table, making the complex processing manageable and interpretable.
Solution Approach 2:
The patent introduces a chip table as an intermediary data structure between the complex feature quantity calculation process and the final visual display. The chip table serves as a mediator that organizes, stores, and presents the calculated feature quantities in a simplified format, reducing the complexity burden on the user interface while maintaining detailed analytical capabilities.
Data Source
AI summary
There is provided a device which may easily and visually judge which chip in an FEM wafer has a normal exposure condition, or which chip has an abnormal exposure condition.A feature quantity for a sectional shape of a resist pattern of an FEM wafer is calculated for each chip region on an FEM wafer using an image of a resist pattern for an FEM wafer. The feature quantity of a sectional shape is displayed for each chip in a chip table of a map representing a position of a chip region on the FEM wafer. Deviations in feature quantities of sectional shapes of resist patterns of a FEM wafer to an appropriate value are displayed in color in the chip table.