Fence Conductors for Sub-Lithographic Interconnects
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Solution Overview
Problem
The reduction in size of patterned conductive lines in semiconductor integrated circuits is limited by existing lithographic processes, which cannot proportionally decrease with the increasing number of transistors, hindering the interconnection of smaller transistors.
Innovation Solution
A method involving the deposition of a first dielectric on a semiconductor substrate, creating trenches, depositing a conductive film within these trenches, and using a second dielectric to form 'fence conductors' by selectively removing portions of the conductive film and dielectric to create ultra-narrow conductive lines that can interconnect active elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If lithographic processes are used to pattern conductive lines, then manufacturing capability is maintained, but the size of conductive lines cannot decrease proportionally with transistor size
Solution Approach 1:
The patent transitions from planar 2D lithographic patterning to 3D vertical patterning by depositing conformal dielectric layers around transistor structures and using anisotropic etching to create vertically oriented conductive lines. This dimensional change allows conductive line size to scale independently of lithographic resolution limits.
Solution Approach 2:
The patent employs self-aligned processes where conformal dielectric deposition automatically creates uniform spacing around transistor structures, and subsequent etching processes use the deposited layers as self-aligned masks. This eliminates the need for separate lithographic alignment steps and enables sub-lithographic feature sizes.
2Productivity
If the number of transistors on a semiconductor die is increased, then circuit functionality is improved, but conductive lines cannot scale down to maintain proportionality
Solution Approach 1:
By moving to 3D vertical conductive structures, the patent enables increased transistor density on the die surface without being constrained by planar conductive line width scaling. The vertical orientation allows conductors to pass through multiple dielectric layers, effectively utilizing the third dimension for interconnection.
Solution Approach 2:
The patent segments the conductive interconnection path into multiple vertical sections separated by dielectric layers, with each section formed through controlled deposition and etching steps. This segmentation allows independent optimization of each conductive segment's dimensions and materials.
3Manufacturing precision
If sub-lithographic pattern sizes are achieved, then interconnection density is enhanced, but new fabrication methods beyond traditional lithography are required
Solution Approach 1:
The patent uses self-aligned conformal deposition and anisotropic etching processes that automatically define pattern dimensions based on the underlying transistor structure geometry. This self-alignment eliminates the need for separate lithographic patterning steps and achieves sub-lithographic precision through material deposition control.
Solution Approach 2:
The patent changes the controlling parameter for feature size from lithographic wavelength to thin film deposition thickness. By controlling the thickness of conformally deposited dielectric layers through atomic layer deposition or chemical vapor deposition, sub-lithographic feature sizes are achieved with precise atomic-layer control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of sub-lithographic patterns of conductive lines, allowing for the interconnection of smaller transistors without the limitations of traditional lithographic processes, enhancing the density and efficiency of semiconductor integrated circuits.
Implementation Method 1
depositing a conductive film on the first dielectric including walls and a bottom of the at least one trench
Implementation Method 2
depositing a conductive film on the first dielectric including walls and a bottom of the at least one trench
Implementation Method 3
removing portions of the conductive film from a face of the first dielectric and the bottom of the at least one trench
Implementation Method 4
depositing a second dielectric between the conductive film on the walls of the at least one trench
Data Source
Figure 1
Figure 2(a)~2(c)
Figure 3(f)~3(d)
AI summary
A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Sub-lithographic patterning of the conductive lines are compatible with existing aluminum and copper backend processing. A first dielectric (212) is deposited onto the semiconductor dice and trenches are formed therein. A conductive film (218) is deposited onto the first dielectric and the trench surfaces. All planar conductive film is removed from the faces of the semiconductor dice and bottoms of the trenches, leaving only conductive films (218) on the trench walls, whereby "fence conductors" are created therefrom. Thereafter the gap between the conductive films on the trench walls are filled in with insulating material (212a). A top portion of the insulated gap fill is thereafter removed to expose the tops of the fence conductors. Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors.